Methodologies for hardware-software co-verification and accelerated virtual emulation.
This paper reviews both SW and UVM Vector Based Verification (VBV) methodologies and Advanced Vector Based Verification (AVBV) that uses Software Defined Networking (SDN) HW to service PCIe transactions to the DUT. When deploying VBV methodologies, using the Veloce Transactor Library (VTL) family of components is most appropriate for UVM, C++ and SDK testbench methodologies.
We explore how VirtuaLAB PCIe and Ethernet Virtual Machines (VM) work together, how they compete for host resources and how VMs address the big device management channel requirements for HW and SW co-verification in Veloce emulation. We also discussed how VMs achieve greater functional coverage using a SDN SW High Availability (HA) test case example. Advanced development considerations highlight how checkpoint save/restore, protocol analyzer, SW configuration flexibility, ease of use and advanced debug features are markedly improved and combined into a single virtualization methodology platform.
Virtual PCIe is the right tool for SDN, accelerating the move to virtual emulation for customers working in this space. Virtual PCIe enables applications to interact with the emulation DUT just as if it there were real silicon sitting on the bench, making it the ideal methodology for HW/SW co-verification.
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