May 2015 - Page 4 of 11 - Semiconductor Engineering

Week 50: It’s Not Just A Technical Conference, It’s An Ecosystem
By Anne Cirkel - 22 May, 2015 - Comments: 0

While our free “I love DAC” registration comes to an end this week, there are still a few weeks left to register for the full conference, the designer and IP track, or one of the many co-located events at DAC (see below). Over the last year I’ve been reminded often about the unique niche occupied by DAC. Just last week a good friend was trying to find an industry event in the greater EDA ... » read more

What’s After 10nm?
By Ed Sperling - 21 May, 2015 - Comments: 0

Prior to 28nm the semiconductor road map was astoundingly predictable. Every two years you could be assured that features would shrink until there were no more atoms left. Two big things and lots of little things later, the trajectory looks much more uncertain. On the large things side are the obvious culprits—EUV delays, and RC delay caused by thinner wires. This is tough science. Pro... » read more

10nm Fab Challenges
By Mark LaPedus - 21 May, 2015 - Comments: 1

After a promising start in 2015, the semiconductor equipment industry is currently experiencing a slight lull. The pause is expected to be short-lived, however. Suppliers of [getkc id="208" comment="3D NAND"] devices are expected to add more fab capacity later this year. And about the same time, foundries are expected to order the first wave of high-volume production tools for 10nm. At 10nm... » read more

The Bumpy Road To 10nm FinFETs
By Mark LaPedus - 21 May, 2015 - Comments: 0

Foundry vendors are currently ramping up their 16nm/14nm [getkc id="185" kc_name="finFET"] processes in the market. Vendors are battling each other for business in the arena, although the migration from planar to finFETs is expected to be a slow and expensive process. Still, despite the challenges at 16nm/14nm, vendors are gearing up for the next battle in the foundry business—the 10nm nod... » read more

How Hard Is FD-SOI Design?
By Ann Mutschler - 21 May, 2015 - Comments: 0

Fully-depleted silicon-on-insulator ([getkc id="220" kc_name="FD-SOI"]) manufacturing technology reached of point of readiness for mass production at the end of March. Along with that, it’s now clear that while there are some impacts on the design flow, those impacts are not game changers. For one thing, the tools required are the same ones currently used for 28nm planar bulk CMOS. The onl... » read more

Waiting For Next-Gen Metrology
By Mark LaPedus - 21 May, 2015 - Comments: 0

Chipmakers continue to march down the various process nodes, but the industry will require new breakthroughs to extend IC scaling at 10nm and beyond. In fact, the industry will require innovations in at least two main areas—patterning and the [getkc id="36" comment="Interconnect"]. There are other areas of concern, but one technology is quickly rising near the top of the list—metrology.... » read more

Addressing Thin Film Thickness Metrology Challenges Of 14nm BEOL Layers
By KLA - 21 May, 2015 - Comments: 0

This paper describes a method to effectively monitor the film stack at different metal CMP process steps using a spectroscopic ellipsometer metrology tool. By proper modeling of the Cu dispersion and simulating the underlayer film information underneath the Cu pad, a single measurement recipe was developed which can be used to monitor each process step in the metal CMP process with stable and r... » read more

10nm Fab Watch
By Mark LaPedus - 21 May, 2015 - Comments: 1

When will the 10nm logic node happen? Analysts believe that foundry vendors will move into 10nm finFET volume production around 2017. Still others say the 10nm finFET ramp could take place anywhere from 2018 to 2020. The predictions are all over the map. One way to predict the timing, progress and demand for 10nm is simple: Follow the fabs. In fact, Intel, Samsung, TSMC and GlobalFound... » read more

Next-Gen Metrology: Searching For A Bright X-Ray Source
By SEMI - 21 May, 2015 - Comments: 0

By Debra Vogler Metrology for semiconductor applications is a broad topic regardless of whether one is talking about front-end-of-line (FEOL) or back-end-of-line (BEOL) technologies. Benjamin Bunday, project manager, CD Metrology and senior member of the technical staff at SEMATECH, broke down the topic of next-generation metrology at 10nm and below into four main categories for SEMI: • I... » read more

Tech Talk: 14nm
By Ed Sperling - 21 May, 2015 - Comments: 0

Tamer Ragheb, digital design methodology technical lead at GlobalFoundries about what's changed with 14nm finFETs, including coloring with double patterning, new corners, Miller Effects, timing issues and variability. [youtube vid=Yk6jSKCtsjU] » read more

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