22nm Process War Begins

Many foundry customers at the 28nm node and above are developing new chips and are exploring the idea of migrating to 16nm/14nm and beyond. But for the most part, those companies are stuck because they can’t afford the soaring IC design costs at advanced nodes.

Seeking to satisfy a potential gap in the market, GlobalFoundries, Intel and TSMC are racing to develop new processes targeted at 22nm. On paper, 22nm enables faster chips than 28nm and is less expensive to develop than 16nm/14nm.

Time will tell whether 22nm will become a popular node like 28nm, or just a niche, but it does give foundry customers some new options. In fact, from separate foundry vendors, customers have the option to select among three different 22nm technologies—planar bulk CMOS, FD-SOI and finFETs.

In the FD-SOI arena, for example, GlobalFoundries is readying its previously-announced 22nm FD-SOI technology for customers. Meanwhile, in another possible option, TSMC recently announced a new 22nm bulk planar process. And then, Intel rolled out a new, low-power version of its 22nm finFET technology.

22nm may not be suitable for everyone, however. As before, customers can stay at 28nm and above, or skip 22nm and move directly to 16nm/14nm and beyond.

All told, there is no one process that fits all applications. Each foundry customer has a different set of requirements for a given IC design. The decision boils down to several metrics, such as power, performance, area scaling, schedule and cost (PPASC).

“The judgment whether to push your product into FD-SOI, finFET (or bulk CMOS) is product specific,” said David Fried, chief technology officer at Coventor. “There are product situations where the answer will be FD-SOI. There are product situations where the answer will be finFETs (and bulk CMOS.)”

To help foundry customers get a handle on the market, Semiconductor Engineering has taken a look at the various technology options at 22nm, including FD-SOI, bulk and finFETs.

Why 22nm?
Not long ago, chip customers simply followed the node progressions and developed products around each technology. But today, there are fewer customers who are following this path, especially since the leading edge of the market shifted from traditional planar processes to finFETs at 16nm/14nm and beyond.

Companies developing chips at the most advanced nodes require the performance benefits of leading-edge processes. Generally, though, analog, mixed-signal, RF and related technologies don’t require advanced nodes.

And demand remains robust for 28nm and above. For example, UMC ended the year in 2016 with a fab utilization rate of more than 90% for both 28nm and 40nm, and nearly 100% for 200mm capacity. “40nm is still very strong,” said Po Wen Yen, chief executive of UMC, in a recent conference call.

Generally, 28nm demand is expected to dip in the first quarter due to normal seasonal issues, but it will bounce back later this year, Yen said. UMC itself has not made any announcements regarding 22nm. UMC is shipping 28nm and has begun ramping up 14nm finFETs. In addition, GlobalFoundries, Samsung and TSMC also offer both 28nm and 16nm/14nm.

Many foundry customers would like to move to advanced nodes, but they can’t justify it. The IC design costs and risks are too high. In total, the average IC design cost for a 16nm/14nm chip is about $80 million, compared to $30 million for a 28nm planar device, according to Gartner. In comparison, it will cost $271 million to design a 7nm chip, according to the firm.

To get a sufficient return on investment, a chip must generate sales that are 10 times greater than the overall design cost, according to International Business Strategies (IBS), a market research firm.

For that reason and others, fewer customers can afford to move to advanced nodes. In fact, there are about 300 foundry customers at 28nm and above, compared to roughly 10 at 10nm/7nm, according to IBS. Of course, the leading-edge foundry customers, such as Apple and Qualcomm, generate enormous volumes for foundries.

“If you can afford $100 million or more for a design, you can maybe go down to 7nm. But many designs cannot do that,” said Handel Jones, chief executive of IBS. “Another key is low power. 16nm finFET gives you low power, but the design is difficult. And you also have a cost premium.”

All told, the 28nm planar node has emerged as the sweet spot for many in the industry, as it combines the right balance of performance, power, area scaling and cost (PPASC) for applications. In fact, despite being introduced several years ago, 28nm will remain viable for some time. It is expected to grow from $10 billion in revenue today to $14 billion by 2025, according to IBS.

Going forward, many customers will end up staying at 28nm and above. Those with deeper pockets may move to 16nm/14nm and beyond.

Then, there are some that want to get a performance boost, but can’t afford 16nm/14nm. For those customers, there is another option—22nm. “28nm will stay there for a long time,” IBS’ Jones said. “We see 22nm being a shrink version of 28nm. Based on the enhancements that you see in terms of performance and area, there is no significant wafer cost (between 28nm and 22nm).”

For that reason, 22nm makes sense, although others have a different view. “I do not believe 22nm will be popular,” said Samuel Wang, an analyst with Gartner. “You have more flavor selections on the mature 28nm node now. Plus, 28nm is selling at very low wafer prices.”

What is FD-SOI?
Regardless, just in case the market takes off, customers must look at the 22nm options. The first player to enter the 22nm race was GlobalFoundries, which nearly two years ago announced a 22nm version of FD-SOI technology. For some time, Samsung has offered 28nm FD-SOI.

FD-SOI is different than traditional bulk CMOS. For example, in bulk CMOS logic, a silicon wafer maker develops a raw wafer. Then, a thin epitaxial layer is grown on the substrate, creating an epi wafer.

In contrast, SOI involves a Smart Cut process, which is developed by Soitec. The process starts with two silicon wafers (A and B). The first wafer (A) is oxidized on top, creating a silicon dioxide insulating layer.

Fig. 1: Smart Cut process. Source: Soitec

Then, hydrogen ions are implanted on the top layer using an ion implanter. This, in turn, creates a weakened layer below the oxide.

The processed wafer (A) is flipped on top of the unprocessed wafer (B). The two wafers are cut in half at the weakened layer. The bottom wafer (B) is annealed and polished, resulting in the final SOI wafer. The other wafer (A) is reused to make another SOI wafer.

Basically, the SOI wafer incorporates a thin insulating layer in the substrate as a means to suppress leakage. The thickness of the insulating layer, or buried oxide layer (BOX), is roughly 20nm to 25nm. “We tend to adjust the thickness based on the request from customers,” said Carlos Mazure, executive vice president and CTO at Soitec.

At the transistor level, meanwhile, there are some similarities and differences between FD-SOI, bulk and finFETs. Both 22nm FD-SOI and 22nm bulk CMOS are planar processes. In a basic planar CMOS process, the transistor has a source and a drain. Current flows from the source to the drain through a channel.

Fig. 2: FD-SOI structure. Source: GlobalFoundries.

In contrast, finFETs are 3D-like structures. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

Planar technology has some issues as the technology approaches at or near 20nm. As chipmakers scale transistors at each node, the channel length becomes shorter. As a result, the channel may suffer from so-called short-channel effects. This, in turn, degrades the sub-threshold slope, or turn-off characteristics, in a device.

Variability is another issue. Basically, a bulk CMOS transistor may perform differently from its nominal behavior in a device. This can produce random differences in terms of threshold voltages. The culprit is a phenomenon called random dopant fluctuation (RDF). RDF is caused by variations of the dopant atoms in the channel.

“In conventional transistors, the channel region below the gate is depleted of mobile charge, leaving the dopant atoms ionized,” said Terry Hook, a senior technical staff member at IBM Research. “The charge from those atoms, along with the gate work function, sets the threshold voltage. The depth of the depletion region controls the electrostatics. Below the depletion region is neutral silicon, with a lot of mobile carriers.”

One way to solve the problem is to move to a fully depleted transistor, namely finFETs and FD-SOI. “RDF affects threshold mismatch and overall leakage as well,” Hook said. “In finFETs and FD-SOI, the channel dopant is minimized and you get a one-time benefit in matching.”

Both FD-SOI and finFETs are better in terms of RDF than bulk, according to Hook. “FD-SOI also has much better short-channel effects than conventional bulk planar, but not as good as finFET,” he said. “FD-SOI requires a thinner body to get to the same electrostatics, because it is gated from one side only, and not two as in finFETs.”

The big selling point for FD-SOI is back-bias. “It has a unique feature of being able to control the threshold voltage by bias and doping in the back-gate,” he said.

Meanwhile, seeking to leverage the benefits of FD-SOI, GlobalFoundries is readying its 22nm FD-SOI technology, dubbed 22FDX. The PDKs are ready and wafer shipments are slated for later this year.

22nm FD-SOI combines finFET performance with the cost of 28nm. It also supports RF and other features. “We chose FD-SOI over bulk planar or finFET because it provides the best combination of performance, power and area for applications,” said Alain Mutricy, senior vice president of the product management group at GlobalFoundries. “Our process is fully qualified for production and we are seeing strong customer demand in high-growth areas such as mobile, IoT and automotive.”

There is room in the market for finFETs, especially for high-end applications. But for low-power devices, FD-SOI makes sense. “Performance comes from a second-generation FD-SOI transistor, which produces nFET (pFET) drive currents of 910μA/μm (856μA/μm) at 0.8 volts,” said Rick Carter, a director at GlobalFoundries, during a presentation at the recent IEDM conference. “For ultra-low power applications, it offers low-voltage operation down to 0.4 volts.”

On the technical front, GlobalFoundries’ 22FDX incorporates a high-k/metal-gate as well as silicon-germanium (SiGe) in the channel for pFET to boost the drive currents, according to an IEDM paper from GlobalFoundries. If required, the SiGe channel can be replaced with silicon to reduce leakage.

22FDX makes use of some double patterning steps. “Dual patterning techniques are used to scale M1/M2 pitch, leading to a logic/SRAM die scaling of 0.72x/0.83x relative to the 28nm poly/SiON technology node,” according to the paper.

While FD-SOI is attractive, there are some issues with the technology. Over the years, FD-SOI has seen relatively limited adoption for several reasons. For one thing, SOI wafer costs are higher. An SOI wafer sells from $370 to $400 each, compared to $100 to $120 for a bulk CMOS wafer, according to IBS.

Then, there are EDA tools for FD-SOI. But customers must devote significant design resources to understand FD-SOI and the nuances of back-bias technology.

So what has held FD-SOI back? “The biggest impediment was the perception that FD-SOI was high cost,” IBS’ Jones said. “Cost was not the issue.”

The big issue is the ecosystem and market pull. Generally, the industry follows Intel and TSMC, both of which back bulk CMOS, not FD-SOI.

But now the tide is turning. “If you look at a year ago compared to today, there has been tremendous progress,” Jones said. “Now, we have test chips out of FD-SOI. You have shipments from NXP and others. And you have committed capacity.”

For example, GlobalFoundries’ FD-SOI fab, based in Dresden, Germany, is capable of producing 65,000 wafers a month. In addition, FD-SOI has a roadmap, as GlobalFoundries is developing 12nm FD-SOI. This process might enable suppliers who are stuck at 16nm/14nm and can’t afford to move to 10nm, 7nm or 5nm.

Bulk CMOS vs finFETs
As before, though, TSMC and Intel are still not backing FD-SOI. “There is no need for it,” said Mark Liu, co-CEO at TSMC, in a recent interview. “The design infrastructure is already there (for bulk CMOS processes).”

For years, TSMC and others have developed traditional bulk CMOS processes. Seeking to extend bulk CMOS and fend off competitive threats from 22nm FD-SOI, TSMC recently introduced a low-power 22nm bulk CMOS process. Compared to 28nm, TSMC’s so-called 22ULP technology offers a 15% performance improvement, or a 35% power reduction, and reduces the die size by up to 10%.

With the process, TSMC is expanding its leading-edge portfolio, offering 28nm, 22nm, 16nm, 12nm, 10nm and 7nm. “They don’t really compete with each other,” Liu said. “We design each of our technologies based on the requirements for customers.”

As for 22nm, however, the technology may encounter some issues, such as short-channel effects or RDF. “There is no room to play with gate dielectric thickness and CD variation,” Gartner’s Wang said. “The real advantage (of 22nm bulk) is questionable.”

Meanwhile, faced with the technical challenges at 20nm planar, TSMC, GlobalFoundries, Samsung and UMC moved to finFETs at 16nm/14nm. In comparison, Intel moved to finFETs at 22nm in 2011.

Fig. 3: Traditional planar transistor. Source: Intel

Fig. 4: Intel’s 22nm Tri-Gate transistor. Source: Intel

Recently, Intel rolled out a new, low-power version of its 22nm finFET technology. Called 22FFL, Intel’s technology is designed for IoT and mobile applications. “(22FFL is) fully RF design enabled and cost-competitive with other industry 28nm and 22nm planar technologies,” said Mark Bohr, senior fellow and director of process architecture and integration at Intel.

For 22nm, finFETs have an advantage over planar, according to Bohr. “FinFET devices are a fully depleted transistor, which have a steeper threshold slope,” he said. “And thus, it can provide lower off state leakage than any planar transistor.”

22FFL combines the features of 22nm and 14nm. For example, Intel’s previous 22nm finFET design had a fin pitch of 60nm and rounded fin shapes. In comparison, its 14nm finFET has a 42nm pitch with tall and narrow fins.

22FFL has a 45nm fin pitch with tall and narrow fins. That fin shape provides better drive currents over rounded fins. In addition, using single patterning techniques, Intel has a more relaxed metal pitch.

Intel’s 22FFL consists of two technologies—high performance and low leakage. It offers a wide range of device features and options. Intel will make the technology available for foundry customers by year’s end.

Fig. 54: 22FFL dimensions. Source: Intel.

22nm finFETs provide better performance, but there are some issues. “FinFET is a relatively high front-end capacitance technology,” Coventor’s Fried said. “FD-SOI may be a significantly lower front-end capacitance solution. Whether front-end capacitance is the biggest problem determines whether you care about FD-SOI or not.”

Of course, customers can stay at 28nm or above. The new nodes, such as 22nm, 12nm and others, give customers more options. The big question is whether any of the new technologies will gain any traction.

Related Stories
Moore’s Law Reset?
Analysis: GlobalFoundries adds 22nm FD-SOI technology, extending benefits of planar design at least two more nodes with improved performance and lower power.
Bulk CMOS Vs. FD-SOI
28nm and 22nm are becoming much more interesting process nodes.