Advanced Materials For High-Temperature Process Integration

From the last several lithography nodes, in the 14 to 10nm range, to the latest nodes, in the 7 to 5nm range, the requirements for patterning and image transfer materials have increased dramatically. One of the key pinch points is the tradeoff between planarization and the high-temperature stability required from carbon films used in patterning and post-patterning process integration.

Patterning process integration typically takes one of two approaches, both of which use a high-temperature hardmask, such as silicon nitride or silicon oxide, deposited with plasma-enhanced chemical vapor deposition (PECVD). In the first scheme, a PECVD hardmask is deposited over a spin-on-carbon (SOC) layer. The resist pattern is transferred into the hardmask, which in turn is used for pattern transfer into the much thicker SOC. In the second approach, once the SOC is patterned as a multi-patterning mandrel, a high-temperature oxide or nitride is applied, using PECVD or atomic layer deposition (ALD), over the carbon mandrel for pattern multiplication. The carbon films are deposited at high temperatures and have the required high-temperature stability. However, these carbon films are conformal in nature and provide minimal planarization.

SOC materials provide a higher degree of planarization versus deposited carbon but, until recently, had limited thermal stability. Though SOCs with high-temperature stability have been available, these typically exhibit film shrinkage of 10% to 30% after the solvent removal bakes and subsequent high-temperature bakes. High shrinkage substantially reduces planarization, as can be seen in a first-generation high-temperature SOC (HT SOC; sample B in figure 1 below). A secondary issue of this shrinkage is the potential for high levels of stress at the film interfaces, which may lead to delamination in subsequent processing. Most HT SOCs are less soluble in dispense solvents than lower-temperature SOCs, requiring more aggressive solvents and in many cases leading to poor common solvent drain compatibility with photoresists, silicon hardmasks (Si HMs), and other lithography materials.

Fig. 1: Comparison of generations of SOC materials for planarization over a wide range of topography line/space bias and gap filling of small high aspect ratio. HT SOCs show planarization after a 450˚C bake while a standard low-temperature (LT) SOC was baked at <350˚C.

Brewer Science’s advanced material development is bringing forth low-shrinkage, high-temperature-stable SOCs with spin-bowl/drain compatibility for advanced node manufacturing and integration. These materials have been tailored for high degrees of planarization, exceeding those of previous generations of lower-temperature SOC materials—such as Sample A from figure 1, upper left and lower left—while presenting less than 2% shrinkage after low-temperature cures of 170°C to high-temperature processing at 450°C. Thermal stability is maintained to 540°C. These SOCs are compatible with high-temperature silicon oxide and silicon nitride PECVD and post-processing (figure 2). By providing both high planarization and high-temperature stability, these advanced SOC materials provide the best combination of properties of vapor-deposited and spin-on carbon materials and therefore provide a higher level of process integration capability with PECVD and etch processes used at EUV and 193nm multi-patterning nodes.

Fig. 2: Top row: PECVD failures are caused by stress in the SOC layer, the coefficient of thermal expansion mismatch, or the outgassing of the SOC underlayer. Bottom row: PECVD of SiO₂ and Si₃N₄ above 300°C showing no defects on HT SOC materials.