Advanced Packaging Moving At Breakneck Pace

Experts at the Table: Semiconductor Engineering sat down to discuss advances in packaging with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion.

L-R: Synopsys’ Roosendaal; ASE’s Chen; Amkor’s Kelly; Promex’s Otte.

SE: What are the big challenges that you’re seeing in packaging these days? What’s changing?

Roosendaal: My focus is mostly on packaging and photonics, and the biggest problem is that the designs are all custom in photonics packaging. There is no standardization. About 80% of the cost that goes into the product is packaging and assembly. So if you make a design, either you pay for a custom package or you use one of the packages offered. But then, if you go to a different packaging house, you’ll have to start again.

Kelly: A somewhat surprising challenge is the pace and the rate of change being driven by AI, and especially large language models. It’s pushing the networking guys and the processor guys to be really nimble, and that’s rippling through literally everything. The 2.5D modules are growing faster in physical size than expected. That manifests itself in stresses and warpage and reliability challenges. These are good challenges, but they’re coming quickly.

Chen: AI hardware is moving fast, but the other thing is the promise of AI. How do we effectively use AI in what we do? And how do we take this opportunity and educate the next generation? Because they’re going to be fully aware of how to do AI, but they may not know how to do packaging. We have this opportunity in building our next generation, or the generation after. It is a tremendous challenge, and we better take good care of it.

Otte: Clearly AI is dominating many things. The thing that strikes me is the rate of obsolescence that is being caused. I suspect we’re going to have massive rebuilding of the contents of these data centers to upgrade the silicon that drives them. There’s going to be massive change. All you have to do is look at the growth in the revenue of NVIDIA. The other trend is we’re starting to see a lot of interest in flex for non-AI devices. There is an increasing number of consumer and individual devices — user-related products such as medical devices and gadgets of various sorts. We will have massive proliferation of a number of these approaches, but a lot of them are not yet being built in any kind of volume.

SE: What do these changes mean for how we go about packaging? Is there any standardization? Will there be assembly design kits that are workable for a long period of time.

Otte: In the AI area, these things are sort of back to the early days of the semiconductor industry, where the semiconductor companies were vertically integrated. As Sander suggested, clearly there’s the increasing demand to go to optical transmission to save power is increasing, but it really is difficult to see how standards are going to arise. There are a few companies like Ayar, and companies like Analog Photonics and a few others working on it. But it hasn’t proliferated widely enough yet for standards to begin to emerge. Optical eventually will become a standard. The benefits are just too great.

Chen: In terms of standardization, you’ve got the users, the equipment suppliers, and the people who do design. They all have to come together for roundtable discussions. This is needed, but it has to happen at the right time. People have to develop their applications, and there will be different group of applications. That’s the path that we need to go forward.

Kelly: We’ve made some progress on standards in the last year. The UCIe specs are out. They’re being vetted in real products today. That defines the routability between chiplets, which helps and is one of the main driving forces for how you’re going to construct a package. If we have more products that have similar bus structures, layer counts, line/space required for signal integrity, etc., that helps consolidate that piece. But back on the silicon photonics, it feels like it’s coming. It must come now because of all the massive data movement. The data centers are having to deal with all these large language models and things like that, but the class leaders are each doing their own thing. They are not taking the same approach.

Roosendaal: It’s very hard, and there are some specialized packaging houses, but they’re not equipped for scaling. And there are huge technical challenges. If you only talk about coupling in the light, you have edge coupling versus gratings. With gratings it’s easier to do the spot conversion, but you have to go out of the plane. Edge coupling has its own challenges. You have to align with micrometer or even sub-micrometer precision depending on the application. And if you’re in multimode, which will eventually cover your angle tolerances also, it is quite restricted. And then there are the thermal properties. These photonic circuits are very sensitive to temperature. And if there’s warpage involved, that affects the angles inside, which is a challenge. That is also what’s driving the high cost because the yields are low.

Chen: We need to have more understanding of the technical solution before we can do standardization. That’s the issue with photonics today.

SE: Turning to chiplets, we have UCIe. Does that mean everything works together?

Kelly: They are working together. There are products with the UCIe bus, so it’s working as advertised. These are all integrated solutions. But the supermarket of chiplets with interoperability among many players is still the idealized goal. There is UCIe and there are a few others, like Bunch of Wires. That is making it a little more democratic, because you have a high-performance bus that everyone can design into.

Chen: I agree. At the recent OCP meeting, people said we need to have solutions that can be used by startups for consumer products.

Kelly: Chiplets got started a while back with the class leaders implementing them for their own products. But now, it’s really interesting to see how far down the slightly lower cost, but high-performance arena, will push into consumer products because that’s super cost-conscious. If you’re talking about handheld devices or even the PC world, they can’t spend the kind of money that somebody would for chiplets for data center products. It will be interesting to see how well the chiplet strategy can work for smaller companies that are trying to save costs and still stay competitive, with cost and performance being the two goals.

Otte: Chiplets ultimately will be an important capability, but I worry about how fast that’s going to happen. I have not seen a chiplet come into our company from any of the hundreds of customers we deal with in a typical year. Chiplets are really only coming out of the big companies. There’s nothing like a merchant market. People are not offering chiplets for sale. You can’t buy an 8 gigahertz memory chiplet. I would expect memory die to be the earliest chiplet implementations. Or maybe an RF device. The low resistances and capacitances are really important.

Chen: Chiplets are being offered in the defense area. There was an early standard called AIB (Advanced Interface Bus).

SE: Isn’t photonics heading into chiplets, as well?

Roosendaal: Definitely. We’ve shown some work we’ve done with TSMC on co-packaged optics. We have an electrical chip as a driver and a photonics die on a flip-chip configuration.

SE: Is the issue there the interface between the electrical and the optical?

Roosendaal: From a design perspective, that interface is challenging. We have tools to make that happen. We have high-frequency extraction to do all the high-frequency parasitics. Temperature is the big issue, and some of those switches on the photonics chips are driven by heaters to maintain a steady temperature. They go hundreds of degrees up and down. But you also want to have it limited to that device, and you don’t want the heat of the electrical to affect the photonic side. You need to simulate system-level heat, and you need to include the package in those simulations. And beyond chiplets, it’s early days for doing die templates. Designers need to know where the ins and outs are, and where to put the alignment waveguides. Another thing you want to do is an alignment-sensitive analysis with the temperature even before you create the software.

Kelly: If you’re talking about getting photonics onto a processor — so-called co-packaged photonics — those processors are all north of 500 watts. Some of them are getting to 1 kilowatt. They have to push all this thermal energy through a very thin package. The temperature distribution in the package is becoming huge. That affects alignment and the net stress inside the package in ways we haven’t seen in the past because we’re trying to get so much power out of a very small area. That’s going to be a big challenge in the future.

Chen: The same is true for 3D packaging. The difficulty is that we can measure the temperature outside the package, but then we need to understand what is really the temperature inside the package. There’s a difference between the actual measurement and a simulated measurement for the inside. It’s the same thing for silicon photonics. Verification of the model is hugely important, but we have to also verify it out in the field. And we have to do that very carefully.

SE: What about on-chip sensors to measure the junction temperature?

Chen: You have to put in more sensors, and that impacts the area.

Roosendaal: There are circuits there for calibration and regulation on the photonics chip. You have to tune it. Also, when you power it on, it takes time to stabilize. That’s another challenge in the design time simulation. You’re doing huge time scales, in microseconds, and you have to go back-time steps in picoseconds. So it’s a big simulation challenge. And the temperature dependence of the device levels is not always fully characterized. The devices also are in full development, so there are many, many variations in the photonics world.

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