Analysis Of Multi-Chiplet Package Designs And Requirements For Production Test Simplification

In recent years there has been a sharp rise of multi-die system designs. Numerous publications targeting a large variety of applications exist in the public domain. One presentation [2] on the IEEE’s website does a good job of detailing the anecdotal path of multi-die systems by way of chiplet building blocks integrated within a single package [2]. The presentation includes references to a handful of example multi-die systems that include artificial intelligence (AI), central processing unit (CPU), field-programmable gate array (FPGA), memory,  analog, radio frequency (RF), input/output (I/O), serializer/deserializer (SERDES), silicon (Si) photonics, etc. It describes advantages and disadvantages of working with chiplets. In addition, it provides package design considerations, including functional and performance aspects. While it serves as good reference material for background, it provides little to no detail for testability. Chapter 8 of the Heterogeneous Integration Roadmap 2019 Edition offers additional packaging details on single chip and multi-chip integration [3].

Outsourced assembly and test (OSAT) houses are in a unique position in the industry since they experience a wide sampling of customer products. Higher volumes and higher mix of products result in a unique perspective of key learning points and missed steps for product packages with multiple die.

Multi-die package

Multi-die package flood gates are open, and the variety and number of custom multi-die packages customers are developing is increasing (see figure 1). Multi-die or heterogeneous die, as the name suggests, are die that may have been fabricated on substrates using completely different wafer fabrication technologies. In most cases, each die within the single die ensemble may represent different functional blocks of the platform or the end application. The end application may require the collection of dice to be integrated within a single package for a variety of reasons, such as the mechanical form and fit in the application or for the overall inter-IC performance, security or efficiencies.

Fig. 1: Multi-die packaging offerings and applications.

The package technologies include substrate-based technologies, redistribution layer (RDL), silicon interposer-based and 3D-stacking-based packaging technologies. Die disaggregation within multi-die packages allows higher levels of integration at the platform level. The building blocks of these packages include Through Silicon Vias (TSVs), substrates, µ-bumps, solder balls, etc. The material type selected for each impacts the electrical performance at test.

Test access & test simplification

OSAT multi-die packages include interconnects between dice, interposers, substrates and solder balls. The challenge for test is to be able to successfully test the dice along with the package interconnect topology. Copper pillar and µ-bump construction determines the contact resistance, steady state and transient power delivery performance. Capacitive loading, crosstalk with material type selection for the substrate and/or the interposer impact data and clock signal path performance. Insertion loss and return loss from interconnect geometries play important roles. Under-fill, end-of-the-line layers, µ-bump, bulk silicon, thermal interface material and heat-spreaders impact the thermal performance.

Fig. 2: Production test for power, data I/O, bias and clocks for multi-die packages. Note: 2.5D and 3D topologies may require different considerations.

Interconnects enable power delivery to all dice within the package. They also enable unidirectional and bidirectional data input/output (I/O) and clocks. These signals may be single ended and/or differential. Also, they may be narrow high speed serial data buses like PCIe or a broadside memory data bus like high bandwidth memory (HBM). There may be unique die features that may have dedicated observability pins that allow logic intellectual property (IP) debug and development. Analog and radio frequency (RF) blocks may require shielding from digital and power supply noise. High-speed operation may generate heat and depending on the logic layout, there may be localized hot spots that may create a thermal gradient across the package. The test environment must allow adequate thermal conductivity to release the generated heat and allow managing the package thermal performance.

Traditional automatic test equipment (ATE) test methodologies are robust to test single die within the package. Test methodologies for multi-die packages have been maturing over the past decade. The complexities of corner cases where the number of Die 2’s interfaces that are not directly exposed externally at the package level have increased by a couple of orders of magnitude within multi-die packages (see figure 3). Test methodologies to address testing all the new corner cases are being implemented and deployed into production testing.

Fig. 3: Production test of a multi-die package with Die 2’s interfaces not exposed externally at the package level for independent testing.

The IEEE 1838 standard enables structural testing with built-in self-test (BIST) using primary and secondary test access ports (TAP) [4]. The on-die design structures enable trapping stuck-at and transient manufacturing defects for die-to-die interfaces and the die-to-package interfaces. Universal Chiplet Interconnect Express (UCIe) is a recently introduced standard that focuses on the specific issues that arise with multiple chiplet integration within the IC package [5].

The first notable production packaging and test simplification that UCIe helps with is constraining the beachfront (shoreline) to a fixed value (see figure 4). Fixed beachfront enables interoperability. It also enables multiple chiplet vendors to provide competing solution options within the platform definition. Higher I/O densities are accomplished with tighter bump pitches and even those preserve interoperability. Finally, the fixed shoreline helps with die layout within the package simplification which enables re-use in manufacturing.

Fig. 4: Fixed shoreline enabled with UCIe specification allows manufacturing package assembly and test simplifications.

The second notable production test simplification that UCIe helps with is lane repair. UCIe requires designs to include multiple redundant lanes. In the corner cases, when there is a defect either in on-die I/O chain or within the package assembly, redundant lanes can be switched in using the repair MUX on the Tx or the Rx during the power-on reset sequence as shown in figure 5.

Fig. 5: Redundant lanes controlled with repair MUXes allow for lane repair during manufacturing work flow.

The third notable production test simplification that UCIe helps with, as of the writing of this paper, is mission mode lane performance parameter monitoring and on-die sensors. The standard requires receivers (Rx) to allow eye margining and characterization (see figure 6). A well calibrated eye health is vital to production testing. On-die process, voltage, temperature (PVT) sensors allow process health indicator (PHI) monitoring of the Si fabrication.

Fig. 6: Signal IO requires eye width and height to meet a minimum specification.

Impacts to production test flows

Traditional production test flows included wafer probe, then die singulation and packaging of a single die within a carefully designed package. Packaged test insertions included burn-in, a couple of final test and quality assurance (QA) test insertions, an optional system level test (SLT) test insertion, perhaps offline binning and fusing and then the post-test marking, inspection and pack/ship steps.

The traditional test flow may not be applicable to multi-die packages and may require revision. Test content redistribution between probe, final test, QA and SLT may need to be architected to allow optimal test coverage through the test flow (see figure 7). Test platform level quality goals for a multi-die system on chip (SoC) may also require redefinition. Advanced design for manufacturing (DFM), design for quality and reliability (DQ&R), design for thermal and design for test (DFT) methods may need to be rearchitected for production simplification and streamlining as well.

Fig. 7: Multi-die optimized high level production test flow.

Call to action

With all the test challenges that advanced customer products present, the ‘call for action’ to the test industry is to design test methods that allow production test simplification by developing standardization and enabling re-use and cost optimization. Test methods that allow feedback into package design and test are expected to accelerate towards technology maturity. Representatives within the Heterogeneous Integration Roadmap team and the IEEE Test Committee with the testability best known methods have continued to encourage the test industry, including OSATs to collaborate, compete and succeed in accelerating the path to technology maturity [6].

To learn more about Amkor’s Test Solutions, visit https://amkor.com/test-services/

References

1. Moore GE (1965) Cramming more components onto integrated circuits
2. Design and Analysis of Chiplet Interfaces for Heterogenous Systems
3. Heterogeneous Integration Roadmap – 2019 Edition
4. IEEE Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits,” IEEE Std 1838-2019 , vol., no., pp.1-73, 13 March 2020, DOI: 10.1109/IEEESTD.2020.9036129
5. UCIe Specification v1.1
6. Heterogeneous Integrated Product Testability Best-Known Methods (BKM)