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Ann Mutschler

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Ann Mutschler is senior executive editor at Semiconductor Engineering.

Author's Latest Posts

The Smartphonification Of Things
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler The term, ‘Internet of Things,’ was first coined more than a decade ago by technology visionary Kevin Ashton but has slowly trickled down to the world of chip design and is now mentioned constantly in conversation. The reason is simple: System-level design tools are getting sophisticated enough to handle the intricacies required by devices in an Internet of ... » read more

More Than Data Management
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler Managing the people, the data and the technology are just as important as meeting the market window given that without these, the entire project wouldn’t function. Throw huge data set sizes, different cultures and business management issues into the mix and the challenges are many. Fortunately, these are issues that the semiconductor industry has been refining for ... » read more

Verifying Your Intent
By Ann Mutschler - 21 Mar, 2013 - Comments: 0

Design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) are physical verification techniques that are mandatory today to check a design and its structures before manufacturing. Checking electrical characteristics of a design is one thing. Verifying power intent is quite another. And the overlap of the two is an intriguing concept. Case in point: Checking fo... » read more

A Balancing Act
By Ann Mutschler - 14 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler If you stay current on data center trends, you are well-versed on the fact that Intel reported last June energy proportionality has effectively doubled server efficiency and workload scaling beyond what Moore’s Law predicted. What does this have to do with power management of SoCs? Cary Chin, director of marketing for low-power solutions at Synopsys, said tha... » read more

Hot Stuff
By Ann Mutschler - 14 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to thermal modeling, which has been practiced for many years, the challenges are daunting. The good news is that approaches are emerging as challenges increased with smaller process nodes and design complexity. Viewed from a number of viewpoints—transistor, chip, package, board and system—thermal models traditionally have been created from m... » read more

Are You A Disrupter?
By Ann Mutschler - 14 Mar, 2013 - Comments: 0

I read a fascinating article recently about how to be a disrupter and how to avoid being disrupted. It goes through the characteristics of a disrupter such as: unencumbered development, unconstrained growth, new product cycles and undisciplined strategy. It also gives the example of how the standalone GPS unit market tanked in a matter of two weeks once smartphone mapping apps became availab... » read more

The New Platform-Based Design
By Ann Mutschler - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Driven by the continued explosion in design costs, the term ‘platform-based design’ is evolving. A platform used to be viewed as an actual chip with some configurability on it that a semiconductor company promoted. Their customers would buy that chip in volume, configure it to their requirements, and sell it inside their end devices. The definition has beco... » read more

The Rise Of Layout-Dependent Effects
By Ann Mutschler - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Designing for today’s advanced semiconductor manufacturing process nodes brings area, speed, power and other benefits but also new performance challenges as a result of the pure physics of running current through tiny wires. Layout-dependent effects (LDE), which emerged at 40nm and are having a larger impact at 28 and 20nm, introduce variability to circuit ... » read more

Good Pattern Flow Ahead For 14, 10nm
By Ann Mutschler - 21 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node. “They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant... » read more

Good Times For Analog Designers
By Ann Mutschler - 14 Feb, 2013 - Comments: 1

By Ann Steffora Mutschler For a number of technological reasons, analog/mixed-signal design and low-power design are converging, and with that comes both challenges and opportunities. As far as challenges go, process variations at 14nm, 20nm and even 28nm have increased significantly to include DFM impacts such as layout-delay effects. On the digital side, those process changes affect... » read more

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