Author's Latest Posts


Dangerous Electricity


Electricity to the modern age is as indispensible as air, but too much can be a bad thing for automotive and aerospace applications—especially when it is in the form of electrostatic discharge (ESD). As chips advance to 28nm, 20nm and 16nm, the design window for electrostatic discharge is shrinking for a number of reasons, explained Norman Chang is vice president and senior product strategis... » read more

The Power Game


By Ann Steffora Mutschler Semiconductor engineering teams always have focused on stepping up performance in new designs, but in the mobile, GPU and tablet markets they’re finding that maintaining the balance between higher performance and the same or lower power is increasingly onerous. The reason: Extreme gaming applications can create scenario files that cause dynamic power consumpt... » read more

Dealing With The Data Glut


By Ann Steffora Mutschler Tools like emulation and simulation are an absolute necessity to design and verify today’s complex SoCs, but what happens when you want to do power analysis and the file sizes are too massive for the emulator to handle? Even with an emulator a five-minute mobile phone call could take three months. Understandably, this issue is causing pain to many design teams... » read more

The Next Limiting Factor


It’s an interesting time in the semiconductor industry. Nodes continue to shrink, we’re on the verge of adopting a new type of transistor (finFET), and there’s also a shift away from planar CMOS – to name a few things on the horizon. What’s also extremely interesting is how design automation and semiconductor manufacturing technology continues to keep the pace with it all. However,... » read more

The Evolving Interconnect


By Ann Steffora Mutschler Chip interconnect protocol requirements are evolving as designs move to 20nm and below process geometries, and not always in predictable ways. At least part of this is being driven by what an SoC is used for. The continued push to shrink features opens up real estate at each new process node. For the past decade, that real estate has been used to add more featu... » read more

The Smartphonification Of Things


By Ann Steffora Mutschler The term, ‘Internet of Things,’ was first coined more than a decade ago by technology visionary Kevin Ashton but has slowly trickled down to the world of chip design and is now mentioned constantly in conversation. The reason is simple: System-level design tools are getting sophisticated enough to handle the intricacies required by devices in an Internet of ... » read more

More Than Data Management


By Ann Steffora Mutschler Managing the people, the data and the technology are just as important as meeting the market window given that without these, the entire project wouldn’t function. Throw huge data set sizes, different cultures and business management issues into the mix and the challenges are many. Fortunately, these are issues that the semiconductor industry has been refining for ... » read more

Verifying Your Intent


Design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) are physical verification techniques that are mandatory today to check a design and its structures before manufacturing. Checking electrical characteristics of a design is one thing. Verifying power intent is quite another. And the overlap of the two is an intriguing concept. Case in point: Checking fo... » read more

A Balancing Act


By Ann Steffora Mutschler If you stay current on data center trends, you are well-versed on the fact that Intel reported last June energy proportionality has effectively doubled server efficiency and workload scaling beyond what Moore’s Law predicted. What does this have to do with power management of SoCs? Cary Chin, director of marketing for low-power solutions at Synopsys, said tha... » read more

Hot Stuff


By Ann Steffora Mutschler When it comes to thermal modeling, which has been practiced for many years, the challenges are daunting. The good news is that approaches are emerging as challenges increased with smaller process nodes and design complexity. Viewed from a number of viewpoints—transistor, chip, package, board and system—thermal models traditionally have been created from m... » read more

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