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Ann Mutschler

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Ann Mutschler is senior executive editor at Semiconductor Engineering.

Author's Latest Posts

Reflecting on the Future
By Ann Mutschler - 13 Jun, 2013 - Comments: 0

Since returning from the Design Automation Conference, I’ve been reflecting on some very interesting discussions I had last week in Austin. The ones that are sticking with me concern the old, sequential algorithms that run EDA tools today. The fact is, given design complexity, they are running out of steam. As a result, the industry is looking at possibly leveraging GPUs since they may be ... » read more

The Growing Need For Behavioral Modeling
By Ann Mutschler - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to behavioral or functional modeling, there is an inherent notion of function, architecture and interconnect. This approach has long been considered a future requirement, but in complex designs the future part no longer applies. Behavioral modeling is a way of isolating or abstracting out a key part of the architectural description and making sure i... » read more

Pitfalls In Subsystem Reuse
By Ann Mutschler - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler IP subsystems provide a ‘divide and conquer’ approach to SoC design by combining multiple IP blocks together to perform individual functions such as audio, graphics or video. The advantage of this approach is that these functions can be tested and verified at the unit level then integrated with the top-level SoC. This also facilitates reuse because each of ... » read more

3D Brings Test Into Fashion
By Ann Mutschler - 16 May, 2013 - Comments: 0

By Ann Steffora Mutschler As integral and critical as test is to the success of an SoC, it isn’t always one of those topics in semiconductor design that seems fashionable. But as Bassilios Petrakis, director of product marketing for test products at Cadence pointed out, “[Test] is not in fashion, but when we hit one of those brick walls then suddenly we have to think how we are going to... » read more

Cost vs. Value
By Ann Mutschler - 10 May, 2013 - Comments: 0

By Ann Steffora Mutschler The increasing amount of mixed-signal content being included in SoCs for automotive, networking and all manner of mobile devices is reinvigorating the mixed-signal industry. While this is great news for companies playing in anything related to mixed-signal technology, it also means increasing complexity for the engineering teams pulling all the pieces together. “... » read more

Bringing Electrical Info To Design’s Forefront
By Ann Mutschler - 09 May, 2013 - Comments: 0

By Ann Steffora Mutschler To reflect the impact on transistors of smaller process nodes and the electrical effects that occur as a result, a shift is underway where the electrical analysis and verification that used to be done when the layout was complete is moving earlier in the design process. The analysis includes parasitic extraction of interconnect and device parasitics, electromigrati... » read more

Lessons Learned In 4G LTE
By Ann Mutschler - 09 May, 2013 - Comments: 0

By Ann Steffora Mutschler While 4G LTE has moved into the mainstream, there are lessons to be learned about these very complex modems, especially from the perspective of balancing power and performance. The road to mainstream wasn’t exactly smooth sailing. “4G LTE initially got a bad rap for battery life, for power consumption,” said Pete Hardee, low-power design solution marketin... » read more

A Poison Apple
By Ann Mutschler - 09 May, 2013 - Comments: 0

As I was researching ‘green’ as it relates to the world of semiconductors I recalled the big story from early 2011 about Apple’s alleged poisoning of workers in China manufacturing plants and wondered whether the situation has changed. At the same time, when I hold my iPhone in my hand, I am sadly aware that my desire for technology might have been at the cost of someone’s health. I ... » read more

Design Topology Requires Physical Data
By Ann Mutschler - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler To best understand a design topology and make decisions on clock/register gating, vector sets are required for the RTL tools to understand how to gate clocks and registers. However, if certain constraints are set on all enabled signals in RTL they can be re-used for gating clocks and registers downstream where enablers are not available—even without needing a ... » read more

Fixing DP Errors: Colors Or Rings
By Ann Mutschler - 18 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler With the move to the 20nm manufacturing node, double patterning (DP) became a requirement. In addition, topology changes occurred that demanded very regular structures, marking a significant departure from 28nm design. As a result of this new approach, new errors are popping up, such as DP violation loops, odd cycle violations and anchor path violations. Certain... » read more

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