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Ann Mutschler

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Ann Mutschler is senior executive editor at Semiconductor Engineering.

Author's Latest Posts

Bringing Electrical Info To Design’s Forefront
By Ann Mutschler - 09 May, 2013 - Comments: 0

By Ann Steffora Mutschler To reflect the impact on transistors of smaller process nodes and the electrical effects that occur as a result, a shift is underway where the electrical analysis and verification that used to be done when the layout was complete is moving earlier in the design process. The analysis includes parasitic extraction of interconnect and device parasitics, electromigrati... » read more

Lessons Learned In 4G LTE
By Ann Mutschler - 09 May, 2013 - Comments: 0

By Ann Steffora Mutschler While 4G LTE has moved into the mainstream, there are lessons to be learned about these very complex modems, especially from the perspective of balancing power and performance. The road to mainstream wasn’t exactly smooth sailing. “4G LTE initially got a bad rap for battery life, for power consumption,” said Pete Hardee, low-power design solution marketin... » read more

A Poison Apple
By Ann Mutschler - 09 May, 2013 - Comments: 0

As I was researching ‘green’ as it relates to the world of semiconductors I recalled the big story from early 2011 about Apple’s alleged poisoning of workers in China manufacturing plants and wondered whether the situation has changed. At the same time, when I hold my iPhone in my hand, I am sadly aware that my desire for technology might have been at the cost of someone’s health. I ... » read more

Design Topology Requires Physical Data
By Ann Mutschler - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler To best understand a design topology and make decisions on clock/register gating, vector sets are required for the RTL tools to understand how to gate clocks and registers. However, if certain constraints are set on all enabled signals in RTL they can be re-used for gating clocks and registers downstream where enablers are not available—even without needing a ... » read more

Fixing DP Errors: Colors Or Rings
By Ann Mutschler - 18 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler With the move to the 20nm manufacturing node, double patterning (DP) became a requirement. In addition, topology changes occurred that demanded very regular structures, marking a significant departure from 28nm design. As a result of this new approach, new errors are popping up, such as DP violation loops, odd cycle violations and anchor path violations. Certain... » read more

Dangerous Electricity
By Ann Mutschler - 11 Apr, 2013 - Comments: 0

Electricity to the modern age is as indispensible as air, but too much can be a bad thing for automotive and aerospace applications—especially when it is in the form of electrostatic discharge (ESD). As chips advance to 28nm, 20nm and 16nm, the design window for electrostatic discharge is shrinking for a number of reasons, explained Norman Chang is vice president and senior product strategis... » read more

The Power Game
By Ann Mutschler - 11 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Semiconductor engineering teams always have focused on stepping up performance in new designs, but in the mobile, GPU and tablet markets they’re finding that maintaining the balance between higher performance and the same or lower power is increasingly onerous. The reason: Extreme gaming applications can create scenario files that cause dynamic power consumpt... » read more

Dealing With The Data Glut
By Ann Mutschler - 11 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Tools like emulation and simulation are an absolute necessity to design and verify today’s complex SoCs, but what happens when you want to do power analysis and the file sizes are too massive for the emulator to handle? Even with an emulator a five-minute mobile phone call could take three months. Understandably, this issue is causing pain to many design teams... » read more

The Next Limiting Factor
By Ann Mutschler - 11 Apr, 2013 - Comments: 0

It’s an interesting time in the semiconductor industry. Nodes continue to shrink, we’re on the verge of adopting a new type of transistor (finFET), and there’s also a shift away from planar CMOS – to name a few things on the horizon. What’s also extremely interesting is how design automation and semiconductor manufacturing technology continues to keep the pace with it all. However,... » read more

The Evolving Interconnect
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler Chip interconnect protocol requirements are evolving as designs move to 20nm and below process geometries, and not always in predictable ways. At least part of this is being driven by what an SoC is used for. The continued push to shrink features opens up real estate at each new process node. For the past decade, that real estate has been used to add more featu... » read more

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