Author's Latest Posts


Your Job is Harder Than Mine


What I do for a living is listen – a lot – and try to make sense of the myriad challenges that I hear about in terms of design and managing power and performance. What you do as an architect, design engineer or verification engineer is live in the trenches with it all, every day. I admire and respect that. This is especially true as I recently pondered and talked with industry luminaries... » read more

Modeling the Future


Every once in a while I read through the employment listings as part of the Semiconductor Manufacturing group on LinkedIn because I find it fascinating to see what employers are looking for even if I am not applying. Particularly for verification engineering position, one of the job responsibilities typically includes development of the architecture for a functional verification environment ... » read more

3D-IC Impact On Computational Lithography?


While 3D devices and technology such as through-silicon vias (TSVs) definitely complicate matters in the design, verification and manufacturing space, one might assume there would also be an impact on the computational lithography tools that are used to ensure printability. Have no fear. Industry experts assure us that this is not the case. Lithography expert Chris Mack acknowledged that ... » read more

Getting In the Ballpark


I admit it; I still have DAC on the brain. Even though attendance may not have been what the exhibitors would have liked to see, the conference is always a fantastic place to discuss ideas and pick up on trends. One topic I discussed with a number of folks are the challenges associated with design today, from the power-performance balance, 3D stacking to new process nodes and complexity, to nam... » read more

Bubble Gum and Scotch Tape


It’s always extremely interesting to talk with actual design engineers, trudging through the trenches of challenges like 3D design. Recently, I was able to speak with Robert Patti, chief technology officer, vice president of design engineering and a director at Tezzaron Semiconductor. The company has been putting 3D designs together for quite some time so I expected to hear that they are u... » read more

Power Modeling: Use Cases Need to be Clearly Defined


By Ann Steffora Mutschler Low-Power/High-Performance Engineering sat down to discuss power modeling during the Design Automation Conference with Vic Kulkarni, senior vice president and general manager at Apache Design; Paul Martin, design enablement and alliances manager at ARM; Sylvan Kaiser, CTO at Docea Power; and Frank Schirrmeister, group director, product marketing for system deve... » read more

Experts At The Table: Black Belt Power Management


By Ann Steffora Mutschler With approximately 80% of SoC content reused from past designs or brought in from internal and external IP sources, a significant part of a design engineer’s job today is writing glue logic and verifying to make sure the integrated system communicates as dictated by the specification. Integration challenges continue to mount with the increasing amount of black ... » read more

Training The Next Gen For Low Power


Reflecting on my time at this year's Design Automation Conference, I am quickly reminded that I work in the most fascinating industry I can think of. Having the opportunity to discuss deep technical low power design issues, forward-looking challenges as well as the business implications face to face with thought leaders is inspiring and invigorating. With the amount of brain power filling Mosco... » read more

Mixed-Signal Integration Drives Platform Chips


Not only are there low-power challenges with just about every design today, there are also very interesting issues concerning integration of mixed-signal onto chips. As chips are get bigger and more costly to develop, many companies are turning to platform chips that can be used in a smartphone and in a tablet with slightly different twists in the functionality of that platform chip because ... » read more

Fundamentals For 3D IC Flows


While true 3D ICs are a few years off, 2.5D is here. There are some key differences, namely that with 2.5D the interposer is a passive die, but there also are some fundamental shared requirements. Samta Bansal, senior product marketing for Silicon Realization at Cadence asserted that first, the digital, custom and package environments must be seamless. “There has to be a co-design between ... » read more

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