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Ann Mutschler

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Ann Mutschler is senior executive editor at Semiconductor Engineering.

Author's Latest Posts

Describing Power Intent
By Ann Mutschler - 08 Sep, 2011 - Comments: 0

Please don’t flame me. I am not aiming this at any one group in particular, but I am always struck at the slowness at which standards efforts move, especially when design teams are the ones really feeling the pain. Case in point: Savita Banerjee, SoC test and verification manager at LSI, told me recently that one of the most important challenges to be solved is a standard way to describe p... » read more

Getting The Balance Right
By Ann Mutschler - 11 Aug, 2011 - Comments: 0

Defining the power architecture for a low-power design means striking a balance between the high-level abstraction and measurements made typically at RTL and below, but today that is easier said than done. “The balance is that at the high level of abstraction, the design choices you make have a big effect over power, yet your ability to measure them is incomplete until you get much further... » read more

Don’t Forget Test
By Ann Mutschler - 11 Aug, 2011 - Comments: 0

In the modeling of designs for power, engineers make sure to include real system modes and get real activity vectors but, according to Pete Hardee at Cadence, there are a few things they are forgetting. “If the only activity you are using is your simulation test vectors, those are probably pretty unrealistic and that’s a big source of error. One other thing we see—and this is quite imp... » read more

Solving Memory Subsystem Bottlenecks In 3D Stacks
By Ann Mutschler - 28 Jul, 2011 - Comments: 0

In today’s do-or-die market environment, many SOC makers strive to differentiate their product based upon the rate at which it performs processing. Closely coupled are power concerns that have led to dominance of a multi-core approach, while economic considerations have resulted in the dominance of the Unified Memory Architecture, where all the processors share access to external DRAM. Stacki... » read more

Aren’t We Beyond That?
By Ann Mutschler - 21 Jul, 2011 - Comments: 0

The latest and greatest technologies always get the most attention because they are new and fresh, but gate-level simulation—a long-time workhorse tool—is seeing a small comeback with designers as of late. According to Cadence’s Pete Hardee, even though the industry is spending a lot of time looking ahead to architectural-level power modeling and virtual prototyping, the need for detai... » read more

Physical Effects Affecting Design
By Ann Mutschler - 16 Jun, 2011 - Comments: 0

With the increase in analog content in today’s designs, the industry is facing a real challenge in terms of how to perform mixed-signal verification at the functional level, at the SPICE level and down to physical implementation of the DRC rules. Joseph Davis, product manager for Calibre interactive and integration products at Mentor Graphics, explained there are three things driving what�... » read more

The Multiple Faces Of Virtual Prototyping
By Ann Mutschler - 28 Apr, 2011 - Comments: 0

Virtual prototyping conjures either confusion or relief, so it should come as no surprise that some chip designers are still confused about the different types of prototypes on the market. “Virtual prototyping is going through a change right now,” explained Gary Smith, founder and chief analyst for Gary Smith EDA. “Today, users are using cycle-based tools to prototype sections of their... » read more

ESL Power Optimization Flow Requires Ecosystem
By Ann Mutschler - 14 Apr, 2011 - Comments: 0

The issue of power optimization today is very painful for many chip architects who are tasked with determining, meeting and holding to a tight power envelope. Questions concerning how well and to what extent power can truly be understood at the architectural level, let alone optimized, are the subject of debate. The ITRS’s most recent projection provides some insight as to current market d... » read more

Wanted: ESL Power Design Flow
By Ann Mutschler - 14 Apr, 2011 - Comments: 0

In order to truly incorporate understanding of power at a higher-than-RTL level of abstraction, a new design flow is needed—and it won’t come from just one vendor. Apache believes that tool flow must contain ESL simulation, ESL synthesis to RTL along with RTL power analysis using ESL simulation results. The company maintains that this very approach has been demonstrated successfully by w... » read more

Design For Configurability
By Ann Mutschler - 17 Mar, 2011 - Comments: 0

I admit it was a bit of a surprise to me to hear from a leading IP provider of the missteps that still befall design teams today as they seek to reuse IP, but it’s a little like rubbernecking. How do you not look? According to Grant Martin, chief scientist at Tensilica, “The biggest thing that people still don’t think about at the beginning of designing some new function is designing i... » read more

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