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Ann Mutschler

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Ann Mutschler is senior executive editor at Semiconductor Engineering.

Author's Latest Posts

Stuck In The Corners
By Ann Mutschler - 24 Feb, 2011 - Comments: 0

It’s common for semiconductor design teams to spend 60% to 70% of product development time on verification, which is why verification has bubbled to the top of the management chain as a concern. Executives worry about the predictability of their product development cycle because so much of it is dependent on successful execution of verification, the ability to achieve coverage closure and the... » read more

The Pain of UPF/CPF
By Ann Mutschler - 10 Feb, 2011 - Comments: 0

Without entering into a debate on the merits of the UPF and CPF, there is a very real and valid concern that designers have today regarding these power intent formats. According to Krishna Balachandran, director of product marketing for low-power verification products at Synopsys, design teams are questioning the validity/correctness of the resulting code. Because they are learning these ... » read more

Tailoring IP, Tools And Flows
By Ann Mutschler - 27 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler As SoC and system complexity rises continually and software drives much more in a system, specific vertical application areas will require tailored IP and tool flows to allow designers to meet time-to-market demands. Today, many systems are designed around a platform, which contains most of the STAR IP—processors, GPUs, memory controllers, interconnects, memory s... » read more

The Challenge Of Packaging
By Ann Mutschler - 13 Jan, 2011 - Comments: 0

Semiconductor packaging isn’t a sexy subject, and it’s one that’s been largely overlooked by the design community. Until now, that is. I recently spoke with Brad Griffin at Cadence, who stressed that managing the power through packages even on a single die is still one of the most challenging things engineers must navigate. “As people integrate more technology into a single chip o... » read more

System-Level Technology Conversations Shift To Deployment
By Ann Mutschler - 16 Dec, 2010 - Comments: 0

While much has been achieved to define a system-level design flow, more is still needed. Technology goals vary depending on the perspective of tool providers in terms of what needs to be done to realize the promise of a streamlined tool flow from TLM 2.0 down to GDS II. To many, 2011 will be an interesting year in the system-level design space as conversations with customers have shifted. �... » read more

Silence Is Golden
By Ann Mutschler - 01 Dec, 2010 - Comments: 0

As the industry continues to march along building devices with ever-increasing battery life, it is necessary to migrate to the latest and greatest process nodes, which as we all know are smaller and use lower voltages. However, any noise in the system—whether it was there before or you start to use something like USB 3.0 or SATA or something else—is actually going to increase the number of ... » read more

Standards Update
By Ann Mutschler - 18 Nov, 2010 - Comments: 0

By Ann Steffora Mutschler In the sometimes-murky waters of system-level modeling standards where real-world adoption can be difficult to track, work is progressing to help hardware and software engineers realize the promise of true hardware-software codesign. The three main standards efforts related to modeling at the system level are OSCI’s TLM-2.0, OCP-IP’s OCP and Open Modeling TAB a... » read more

Reducing Bottlenecks
By Ann Mutschler - 18 Nov, 2010 - Comments: 0

By Ann Steffora Mutschler For the first time ever, China recently earned fastest supercomputer bragging rights with its Tianhe-1A supercomputer, which can perform 2.57 quadrillion computing operations per second. The machine has been successfully used to survey mines, forecast weather and design high-end machinery. While it has caused concern, it is important to note that the Tianhe-1A use... » read more

Making Power Delivery Networks Better
By Ann Mutschler - 04 Nov, 2010 - Comments: 0

Careful design of power delivery networks can make the difference in whether a chip manages power effectively or fails completely. This impact of cost and other factors in the design process has not gone unnoticed. Aveek Sarkar, vice president of customer support and product engineering at Apache Design Solutions, pointed to the iPhone as an example, where 50% or more of the bill of material... » read more

Best Practices For Multicore SoC Test And Debug
By Ann Mutschler - 21 Oct, 2010 - Comments: 0

By Ann Steffora Mutschler In increasingly complex SoC designs, many of which contain multiple cores and multiple modes, determining best practices for testing and debugging is a moving target. Jason Andrews, architect at Cadence Design Systems, said multicore debug is a huge issue. It isn’t easy to do, and there aren’t many good ways to do it. He suggested one approach is to try to u... » read more

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