Author's Latest Posts


28nm FinFETs?


One star of the upcoming 14/16nm process node is the introduction of the finFET, a fundamentally new transistor that overcomes many of the limitations associated with planar transistors. While these devices are more complex to construct—and the physical extraction processes associated with them is more complex due to an increased number of resistances and capacitances—they are seen as a tra... » read more

Moore’s Law Tail No Longer Wagging The Dog


In a recent special report titled “Will 7nm and 5nm really happen?” Semiconductor Engineering outlined the progress being made for new production nodes and the progress being made to overcome the technological challenges that they contain. But who are the likely candidates for those new nodes and who is going to pay for their development, including the EDA tools that will be necessary to ut... » read more

Programming Is Not Patentable


I have written about problems with the [getkc id="16" kc_name="patent"] systems several times in the past and have also talked about a very important case that has been making its way through the courts. This one case, Alice Corp versus CLS, has been particularly closely followed because of the importance of its conclusion on software patents. On June 19 the Supreme Court came to its conclusion... » read more

Without Moore’s Law: EDA


Semiconductor Engineering is examining the assertion about the end of Moore’s Law in a number of different ways. The special report, “Will 7nm and 5nm really happen?” looked at the technical aspects related to continuing into finer geometries. “Moore’s Law Tail No Longer Wagging the Dog” asked the question about the economics of people being able to afford to go to the latest node. ... » read more

Tougher Memory Choices


In part 1 of this roundtable, the participants talked about the investments being made in memory technologies, the role that memories play in system security and the tools support for optimizing memory architecture. Taking part in the conversation are Herbert Gebhart vice president of interface and system solutions in the Memory and Interfaces Division of Rambus, Bernard Murphy, chief technolog... » read more

Tougher Memory Choices


Memories have become a hot topic, so Semiconductor Engineering sat down with experts during DAC to discuss some of the issues. Taking part in the conversation were Herbert Gebhart vice president of interface and system solutions in the Memory and Interfaces Division of Rambus, Bernard Murphy, chief technology officer for Atrenta; Patrick Soheili, vice president and general manager for IP Soluti... » read more

Beyond The DAC Keynote


The Design Automation Conference is split into a number of tracks, such as IP, automotive, embedded software and security, and these overlay the main EDA track. One of these themes overlays the first day of DAC, and this year that honor goes to IP. That means that the first keynote of the conference comes from the IP industry, and this is rather fitting given the importance IP is having for ... » read more

DAC Day One


The Design Automation Confeence got off to a roaring start today and the Synopsys breakfast and keynote were standing room only. The Synopsys breakfast brought together foundry (Samsung), IP developer (Arm) and tool provider (Synopsys) to talk about the growing requirements of ecosystems and partnership in order to make new processes available for production usage. Perhaps the most surprisin... » read more

Opening Salvo At DAC


As always, DAC starts with a view of the state of the industry from Gary Smith and this year, Smith's view was a little different from previous years. For DAC 51, Smith no longer spoke of ESL as being the key to the future. In fact, he conceded that he may have been off a few years or a couple of decades on that one, but in the end he was right. This year his main message seemed to be that k... » read more

Executive Insight: Adnan Hamid


Semiconductor Engineering sat down with Adnan Hamid, founder and CEO of Breker Verification Systems. Breker was founded in 2003 and has been concentrating on the creation of verification methodologies for multiprocessor SoCs using graph-based entry methods – something that became a hot topic at DVCon 2014 after Mentor Graphics decided to donate its format to Accellera for standardization. ... » read more

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