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Brian Bailey

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Brian Bailey is Technology Editor/EDA for Semiconductor Engineering.

Author's Latest Posts

Beyond The DAC Keynote
By Brian Bailey - 12 Jun, 2014 - Comments: 1

The Design Automation Conference is split into a number of tracks, such as IP, automotive, embedded software and security, and these overlay the main EDA track. One of these themes overlays the first day of DAC, and this year that honor goes to IP. That means that the first keynote of the conference comes from the IP industry, and this is rather fitting given the importance IP is having for ... » read more

DAC Day One
By Brian Bailey - 03 Jun, 2014 - Comments: 0

The Design Automation Confeence got off to a roaring start today and the Synopsys breakfast and keynote were standing room only. The Synopsys breakfast brought together foundry (Samsung), IP developer (Arm) and tool provider (Synopsys) to talk about the growing requirements of ecosystems and partnership in order to make new processes available for production usage. Perhaps the most surprisin... » read more

Opening Salvo At DAC
By Brian Bailey - 02 Jun, 2014 - Comments: 0

As always, DAC starts with a view of the state of the industry from Gary Smith and this year, Smith's view was a little different from previous years. For DAC 51, Smith no longer spoke of ESL as being the key to the future. In fact, he conceded that he may have been off a few years or a couple of decades on that one, but in the end he was right. This year his main message seemed to be that k... » read more

Executive Insight: Adnan Hamid
By Brian Bailey - 22 May, 2014 - Comments: 1

Semiconductor Engineering sat down with Adnan Hamid, founder and CEO of Breker Verification Systems. Breker was founded in 2003 and has been concentrating on the creation of verification methodologies for multiprocessor SoCs using graph-based entry methods – something that became a hot topic at DVCon 2014 after Mentor Graphics decided to donate its format to Accellera for standardization. ... » read more

The Circle Of Test And EDA Is Complete
By Brian Bailey - 22 May, 2014 - Comments: 1

For those of you who were around and involved with EDA back in the early ’80s, you may remember that chip design was not the focus. It was the board that received most of the attention. Chips were small and did not require much in the way of functional verification. [getkc id="29" kc_name="Synthesis"] had not been invented and so gate-level design was where everything happened, and much of th... » read more

Big Memory Shift Ahead
By Brian Bailey - 22 May, 2014 - Comments: 1

System architecture has been driven by the performance of [getkc id="22" kc_name="memory"]. Processor designers would have liked all of the memory be fast [getkc id="92" kc_name="SRAM"], placed on-chip for maximum performance, but that was not an option. Memory had to be fabricated as separate chips and connected via a Printed Circuit Board (PCB). That limited the number of available I/O ports ... » read more

Is Formal Ready To Displace Simulation?
By Brian Bailey - 21 May, 2014 - Comments: 2

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In part two, the panel focused on the subject of coverage and the ways in which formal coverage can be combined with simulation. In this segment we start exploring the impact that sequential equi... » read more

Can HLS Be Trusted?
By Brian Bailey - 08 May, 2014 - Comments: 1

Semiconductor Engineering sat down with Mike Meredith, solutions architect at Cadence/Forte Design Systems; Mark Warren, Solutions Group director at Cadence; Thomas Bollaert, vice president of application engineering at Calypto; and Devadas Varma, senior director at Xilinx. Part 1 of the discussion looked at the changing market for HLS and the types of customers who are adopting HLS today. Divi... » read more

Powerful Memories
By Brian Bailey - 07 May, 2014 - Comments: 1

Memory consumes more of the surface area of a die than any other component. So what changes have happened over the past few years to reduce the power consumption of memories, and where are the big opportunities for saving power? Let's take a closer look. A Growing Concern One of the key drivers for SoCs is the desire to reduce product costs, reduce form factors, reduce power, increase perfo... » read more

Graphing Toward Standardization
By Brian Bailey - 24 Apr, 2014 - Comments: 0

Graph-based verification has become the hot topic of the day. It commanded a lot of attention at the recent DVCon, promises to fix many of the problems plaguing functional verification, can provide an automated way to perform system-level verification, enables portability of tests between simulation, emulation and prototyping, reduces the wastage created by constrained random test pattern gener... » read more

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