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Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.

Author's Latest Posts

Designing Hardware For Security
By Ed Sperling - 09 May, 2018 - Comments: 1

By Ed Sperling and Kevin Fogarty Cyber criminals are beginning to target weaknesses in hardware to take control of devices, rather than using the hardware as a stepping stone to access to the software. This shift underscores a significant increase in the sophistication of the attackers, as evidenced by the discovery of Spectre and Meltdown by Google Project Zero in 2017 (made public in Ja... » read more

The Case For Chiplets
By Ed Sperling - 07 May, 2018 - Comments: 4

Discussion about chiplets is growing as the cost of developing chips at 10/7nm and beyond passes well beyond the capabilities of many chipmakers. Estimates for developing 5nm chips (the equivalent 3nm for TSMC and Samsung) are well into the hundreds of millions of dollars just for the NRE costs alone. Masks costs will be in the double-digit millions of dollars even with EUV. And that's assum... » read more

Rules Of The Driverless Road
By Ed Sperling - 03 May, 2018 - Comments: 0

The growing disparity among states, countries and carmakers over autonomous driving is turning what should be a logical progression into chaos. Consider what's happening in California, which is determined to remain the leader in this tech revolution. The state last month relaxed its testing rules so that cars can be monitored remotely, with no driver actually present inside the car. I... » read more

Tech Talk: HW Security
By Ed Sperling - 03 May, 2018 - Comments: 0

Ben Levine, senior director of product management at Rambus, explains how to minimize the risk of attacks on chip hardware, why design for security is becoming more critical for connected devices, and strategies for making devices less vulnerable. https://youtu.be/twgHcdqvyjU » read more

Tech Talk: eFPGA Timing
By Ed Sperling - 03 May, 2018 - Comments: 0

Flex Logix's Chen Wang talks about timing for an embedded FPGA and how that differs from ASIC timing. https://youtu.be/n88D1N4IEbs » read more

Finding And Fixing ML’s Flaws
By Ed Sperling - 02 May, 2018 - Comments: 0

OneSpin CEO Raik Brinkmann sat down with Semiconductor Engineering to discuss how to make machine learning more robust, predictable and consistent, and new ways to identify and fix problems that may crop up as these systems are deployed. What follows are excerpts of that conversation. SE: How do we make sure devices developed with machine learning behave as they're supposed to, and how do we... » read more

The Great Chip Shakeup
By Ed Sperling - 26 Apr, 2018 - Comments: 2

Facebook, Alibaba, Google, Apple and Samsung are all designing their own chips. So are Cisco and Huawei. So what exactly does this mean for big chipmakers and the semiconductor ecosystem? While your first impulse might be to draw a straight line between Qualcomm's decision to cut 1,500 jobs and reports about giant systems companies developing chips in-house, it's not clear there is any corre... » read more

Tech Talk: FPGA RTL Checking
By Ed Sperling - 26 Apr, 2018 - Comments: 3

Tobias Welp, software architect and engineering manager at OneSpin Solutions, explains how to ensure the RTL created by design engineers matches what shows up in an FPGA. https://youtu.be/0N1PDYyq0dY » read more

Mashup At 7nm
By Ed Sperling - 19 Apr, 2018 - Comments: 0

The merger of two standards organizations typically falls well below the radar of most engineers, but folding the ESD Alliance (formerly known as the EDA Consortium) into SEMI is a different kind of deal. Ever since the introduction of finFETs and multiple patterning, EDA tools have become an integral part of the development of new manufacturing processes. Without those tools, there is no po... » read more

Design Rule Complexity Rising
By Ed Sperling - 19 Apr, 2018 - Comments: 0

Variation, edge placement error, and a variety of other issues at new process geometries are forcing chipmakers and EDA vendors to confront a growing volume of increasingly complex, and sometimes interconnected design rules to ensure chips are manufacturable. The number of rules has increased to the point where it's impossible to manually keep track of all of them, and that has led to new pr... » read more

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