Author's Latest Posts

Quantifying Rowhammer Vulnerability for DRAM Security
By Technical Paper Link - 14 Mar, 2022 - Comments: 0

Abstract: "Rowhammer is a memory-based attack that leverages capacitive-coupling to induce faults in modern dynamic random-access memory (DRAM). Over the last decade, a significant number of Rowhammer attacks have been presented to reveal that it is a severe security issue capable of causing privilege escalations, launching distributed denial-of-service (DDoS) attacks, and even runtime attack ... » read more

Designing a 2048-Chiplet, 14336-Core Waferscale Processor
By Technical Paper Link - 14 Mar, 2022 - Comments: 0

Abstract "Waferscale processor systems can provide the large number of cores, and memory bandwidth required by today’s highly parallel workloads. One approach to building waferscale systems is to use a chiplet-based architecture where pre-tested chiplets are integrated on a passive silicon-interconnect wafer. This technology allows heterogeneous integration and can provide significant perfor... » read more

The Migration of Engine ECU Software From Single-Core to Multi-Core
By Technical Paper Link - 14 Mar, 2022 - Comments: 0

Abstract "As multiple functions have been added to single-core-based engine electronic control units (ECUs) in vehicles, automotive researchers and manufacturers have actively studied multi-core architecture for engine ECUs. Multi-core architecture can provide load balancing and parallelism that can meet the requirements of international organization standard (ISO) 26262. However, since real-w... » read more

Benchmarking Memory-Centric Computing Systems: Analysis of Real Processing-in-Memory Hardware
By Technical Paper Link - 10 Mar, 2022 - Comments: 0

Abstract "Many modern workloads such as neural network inference and graph processing are fundamentally memory-bound. For such workloads, data movement between memory and CPU cores imposes a significant overhead in terms of both latency and energy. A major reason is that this communication happens through a narrow bus with high latency and limited bandwidth, and the low data reuse in memory-bo... » read more

QubiC: An Open-Source FPGA-Based Control and Measurement System for Superconducting Quantum Information Processors
By Technical Paper Link - 09 Mar, 2022 - Comments: 0

Abstract: "As quantum information processors grow in quantum bit (qubit) count and functionality, the control and measurement system becomes a limiting factor to large-scale extensibility. To tackle this challenge and keep pace with rapidly evolving classical control requirements, full control stack access is essential to system-level optimization. We design a modular field-programmable gate a... » read more

Pinpointing the Dominant Component of Contact Resistance to Atomically Thin Semiconductors
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract "Achieving good electrical contacts is one of the major challenges in realizing devices based on atomically thin two-dimensional (2D) semiconductors. Several studies have examined this hurdle, but a universal understanding of the contact resistance and an underlying approach to its reduction are currently lacking. In this work we expose the shortcomings of the classical contact resist... » read more

SparseP: Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Systems
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract "Several manufacturers have already started to commercialize near-bank Processing-In-Memory (PIM) architectures. Near-bank PIM architectures place simple cores close to DRAM banks and can yield significant performance and energy improvements in parallel applications by alleviating data access costs. Real PIM systems can provide high levels of parallelism, large aggregate memory bandwi... » read more

Zero-Bias Power-Detector Circuits based on MoS2 Field-Effect Transistors on Wafer-Scale Flexible Substrates
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract: "We demonstrate the design, fabrication, and characterization of wafer-scale, zero-bias power detectors based on two-dimensional MoS2 field effect transistors (FETs). The MoS2 FETs are fabricated using a wafer-scale process on 8 μm thick polyimide film, which in principle serves as flexible substrate. The performances of two CVD-MoS2 sheets, grown with different processes and showi... » read more

Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract:  "The expansive globalization of the semiconductor supply chain has introduced numerous untrusted entities into different stages of a device’s lifecycle, enabling them to compromise its security. To make matters worse, the increasing complexity in the design as well as aggressive time-to-market requirements of the newer generation of integrated circuits can lead either designers t... » read more

Advances in Logic Locking: Past, Present, and Prospects
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract: "Logic locking is a design concealment mechanism for protecting the IPs integrated into modern System-on-Chip (SoC) architectures from a wide range of hardware security threats at the IC manufacturing supply chain. Logic locking primarily helps the designer to protect the IPs against reverse engineering, IP piracy, overproduction, and unauthorized activation. For more than a decade,... » read more

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