Author's Latest Posts


Channel-Last GAA NS Oxide FET (Stanford, TSMC, ETH Zurich et al.)


A new technical paper titled "Channel-last gate-all-around nanosheet oxide semiconductor transistors" was published by researchers at Stanford University, TSMC, ETH Zurich, SLAC National Accelerator Laboratory, and Polish Academy of Sciences. Abstract "As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the t... » read more

DL Atomistic Semi-Empirical Pseudopotential Model For Nanomaterials (UC Berkeley, LBNL et al.)


A new technical paper titled "Deep-learning atomistic semi-empirical pseudopotential model for nanomaterials" was published by researchers at UC Berkeley, Lawrence Berkeley National Laboratory et al. Abstract "The semi-empirical pseudopotential method (SEPM) has been widely applied to provide computational insights into the electronic structure, photophysics, and charge carrier dynamics of ... » read more

Study Of HW Acceleration for Neural Networks (Arizona State Univ.)


A new technical paper titled "Hardware Acceleration for Neural Networks: A Comprehensive Survey" was published by researchers at Arizona State University. Abstract "Neural networks have become a dominant computational workload across cloud and edge platforms, but their rapid growth in model size and deployment diversity has exposed hardware bottlenecks that are increasingly dominated by mem... » read more

Exploiting Domain Wall Conduction in Nitride Ferroelectrics As A New Type of Memristive FeRAM (Kiel Univ., Fraunhofer, NaMLab, TU Dresden)


A new technical paper titled "Nitride Ferroelectric Domain Wall Memory for Next-Generation Computing" was published by researchers at Kiel University, Fraunhofer Institute for Silicon Technology (ISIT), NaMLab, and TU Dresden. Abstract "The emerging nitride ferroelectrics, such as Al1-xScxN promise to significantly advance our current information technology. In particular, two-terminal mem... » read more

Scalable AI/ML Method For Improved MTJ Performance (UT Austin, TSMC, TDK Headway)


A new technical paper titled "LEAD: Literature Enhanced Ab Initio Discovery of Nitride Dusting Layers for Enhanced Tunnel Magnetoresistance and Lower Resistance Magnetic Tunnel Junctions" was published by researchers at University of Texas at Austin, TSMC, and TDK Headway Technologies Inc. Abstract "Magnetic tunnel junctions (MTJs) using magnesium oxide (MgO) tunnel barriers face challenges... » read more

Reliability Extension Architecture For Cost-Effective HBM (RPI, ScaleFlux, IBM TJ Watson)


A new technical paper titled "Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference" was published by researchers at Rensselaer Polytechnic Institute, ScaleFlux and IBM T.J. Watson Research Center. Abstract "LLM inference is increasingly memory bound, and HBM cost per GB dominates system cost. Current HBM stacks include short on-die ECC that tightens binning, raise... » read more

Two-Stage Hardware Fuzzer (TU Darmstadt)


A new technical paper titled "GoldenFuzz: Generative Golden Reference Hardware Fuzzing" was published by researchers at TU Darmstadt. Abstract "Modern hardware systems, driven by demands for high performance and application-specific functionality, have grown increasingly complex, introducing large surfaces for bugs and security-critical vulnerabilities. Fuzzing has emerged as a scalable sol... » read more

MoS2 Memristors With Fast Switching Speed and Low Power Consumption (AMO, RWTH Aachen et al.)


A new technical paper titled "Intermediate Resistive State in Wafer-Scale Vertical MoS2 Memristors Through Lateral Silver Filament Growth for Artificial Synapse Applications" was published by researchers at AMO GmbH, RWTH Aachen, Forschungszentrum Jülich, Peter Grünberg Institute, Eindhoven University of Technology et al. Abstract "Memristors based on 2D materials have garnered signifi... » read more

The Impact Of DRAM Writes On DDR5-Based Systems (Georgia Tech)


A new technical paper titled "BARD: Reducing Write Latency of DDR5 Memory by Exploiting Bank-Parallelism" was published by Georgia Tech. Abstract "This paper studies the impact of DRAM writes on DDR5-based system. To efficiently perform DRAM writes, modern systems buffer write requests and try to complete multiple write operations whenever the DRAM mode is switched from read to write. Whe... » read more

AFM-Based Protocol for Characterizing the Incipient Stages of Plasticity on Hybrid Bonding-Ready Copper Pads (NIST, Intel, Colorado School of Mines)


A new technical paper titled "Probing the Nanoscale Onset of Plasticity in Electroplated Copper for Hybrid Bonding Structures via Multimodal Atomic Force Microscopy" was published by researchers at the National Institute of Standards and Technology, Intel, and Colorado School of Mines. Excerpt  "The slowdown of Moore’s law has elicited a paradigm shift whereby shrinking of in-plane dim... » read more

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