Author's Latest Posts

PGIREM: Reliability-Constrained IR Drop Minimization and Electromigration Assessment of VLSI Power Grid Networks using Cooperative Coevolution
By Technical Paper Link - 31 Dec, 2018 - Comments: 0

Abstract "Due to the resistance of metal wires in power grid network, voltage drop noise occurs in the form of IR drop which may change the output logic of underlying circuits and may affect the reliability performance of a chip. Further, it is necessary to handle different reliability constraints while designing a robust power grid network for a chip. Any violation of such constraints may inc... » read more

Machine Learning Based Prediction: Health Behavior on BP
By Technical Paper Link - 12 Oct, 2018 - Comments: 0

Source: UC San Diego Jacobs School of Engineering, Po-Han Chiang and Sujit Dey, Mobile Systems Design Lab, Dept. of Electrical and Computer Engineering Using wearable off-the-shelf technology and machine learning, UC San Diego researchers have developed a method to predict an individual’s blood pressure and provide personalized recommendations to lower it based on this data. The researc... » read more

Autonomous Vehicle Navigation in Rural Environments without Detailed Prior Maps (MIT)
By Technical Paper Link - 15 May, 2018 - Comments: 0

Source: MIT CSAIL: Teddy Ort, Liam Paul, Daniela Rus According to MIT Computer Science and Artificial Intelligence Laboratory (CSAIL) researchers, navigating roads less traveled in self-driving cars is a difficult task mainly because self-driving cars are usually only tested in major cities where countless hours have been spent meticulously labeling the exact 3D positions of lanes, curbs, of... » read more

Switching a Perpendicular Ferromagnetic Layer by Competing Spin Currents
By Technical Paper Link - 31 Mar, 2018 - Comments: 0

ABSTRACT "An ultimate goal of spintronics is to control magnetism via electrical means. One promising way is to utilize a current-induced spin-orbit torque (SOT) originating from the strong spin-orbit coupling in heavy metals and their interfaces to switch a single perpendicularly magnetized ferromagnetic layer at room temperature. However, experimental realization of SOT switching to date req... » read more

Silicon CMOS Architecture For A Spin-based Quantum Computer
By Technical Paper Link - 24 Jan, 2018 - Comments: 1

Source: UNSW Sydney Authors: M. Veldhorst (1,2),  H.G.J. Eenink (2,3) , C.H. Yang (2), and A.S. Dzurak (2) 1 Qutech, TU Delft, The Netherlands 2 Centre for Quantum Computation and Communication Technology, School of Electrical Engineering and Telecommunications,UNSW, Sydney, Australia 3 NanoElectronics Group, MESA+ Institute for Nanotechnology,University of Twente, The Netherlands Te... » read more

Overlay Control for Nanoimprint Lithography
By Technical Paper Link - 31 Dec, 2017 - Comments: 0

Abstract:  Nanoimprint lithography (NIL) is a promising technique for fine-patterning with a lower cost than other lithography techniques such as EUV or immersion with multi-patterning. NIL has the potential of "single" patterning for both line patterns and hole patterns with a half-pitch of less than 20nm. NIL tools for semiconductor manufacturing employ die- by-die alignment syste... » read more

Overlay Control for Nanoimprint Lithography
By Technical Paper Link - 31 Dec, 2017 - Comments: 0

Abstract: Nanoimprint lithography (NIL) is a promising technique for fine-patterning with a lower cost than other lithography techniques such as EUV or immersion with multi-patterning. NIL has the potential of "single" patterning for both line patterns and hole patterns with a half-pitch of less than 20nm. NIL tools for semiconductor manufacturing employ die- by-die alignment system ... » read more

Adaptive Test With Test Escape Estimation for Mixed-Signal ICs
By Technical Paper Link - 31 Dec, 2017 - Comments: 0

Abstract: The standard approach in industry for post-manufacturing testing of mixed-signal circuits is to measure the performances that are included in the data sheet. Despite being accurate and straightforward, this approach involves a high test time since there are numerous performances that need to be measured sequentially by switching the circuit into different test configurations. Adapt... » read more

Using Run-Time Reverse-Engineering to Optimize DRAM Refresh
By Technical Paper Link - 31 Dec, 2017 - Comments: 0

Abstract: "The overhead of DRAM refresh is increasing with each density generation. To help offset some of this overhead, JEDEC designed the modern Auto-Refresh command with a highly optimized architecture internal to the DRAM---an architecture that violates the timing rules external controllers must observe and obey during normal operation. Numerous refresh-reduction schemes manually refresh ... » read more

Making high-capacity data caches more efficient
By Technical Paper Link - 24 Oct, 2017 - Comments: 4

Source: Researchers from MIT, Intel, and ETH Zurich Xiangyao Yu (MIT), Christopher J. Hughes (Intel), Nadathur Satish (Intel) Onur Mutlu (ETH Zurich), Srinivas Devadas (MIT) Technical Paper link MIT News article As the transistor counts in processors have gone up, the relatively slow connection between the processor and main memory has become the chief impediment to improving comp... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy