Benefits And Challenges In Multi-Die Assemblies

Experts at the Table: Semiconductor Engineering sat down to discuss chiplets, hybrid bonding, and new materials with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion. To view part one of this discussion, click here. Part two is here.

L-R: Synopsys’ Roosendaal; ASE’s Chen; Amkor’s Kelly; Promex’s Otte.

SE: For years, automotive chips were not developed at the leading edge, but all of that has changed with electric vehicles and state-of-the-art infotainment. What problems are you seeing?

Kelly: The high-end ADAS needs processors that are 5nm or smaller to be competitive. Once you’re at 5nm, you look at the wafer cost, and you’re going to think seriously about a chiplet approach because you can’t build a big die in 5nm. And the yield is low enough that it’s tremendously expensive. If you’re in 5nm or below, the customer is always thinking about taking a piece of a 5nm chip instead of the whole die and spending more on the package. ‘Is it going to be a lower-cost option to get my performance than trying to do it all in one one bigger die?’ So yes, the high end auto guys definitely are looking at chiplets. The class leaders are all looking at it. It’s two or three or four years later than compute, whether that’s PCs or data centers, but it’s definitely out there. They want the reliability, so you’ve got to prove that. But it’s definitely coming.

Chen: I don’t see a I don’t see a big roadblock. I see a lot of learning and understanding the qualification. It goes back to metrology. How do we make packages that pass the qualification we need for the very strict automotive standards? But it’s coming.

SE: With all these thermal issues and growing complexity of these multi-die assemblies, are there new kinds of stress testing profiles or different types of tests? Or does do the current JEDEC standard cover an integrated system like that?

Chen: What I see is that we need to develop better diagnostics so we understand what fails. We’ve discussed metrology coming together diagnostics, and it’s our responsibility to figure out how we can build a more robust package, with more robust materials and processes, and prove them.

Kelly: We have case studies with customers today where they are learning things from their system-level tests — functional board tests, especially with regard to temperature effects, that you just can’t see in a JEDEC test. That’s just an isothermal test. ‘It’s hot, it’s cold, it’s transitioning.’ But the temperature distribution in the package is nowhere near representative of the real world. More customers want to do system level testing earlier because they’re aware of this fact — but not everybody. Simulation comes into this, as well. If you get really good at your thermal-mechanical combined simulations, then it’s easier to take a look at the problem analytically because you know what to look for in your testing. They go hand-in-hand. But it’s still early in that trend.

SE: At mature technology nodes, are there more thermal issues to deal with than in the past?

Otte: Yes, but the one that keeps popping up in the last year or two is co-planarity. We’re seeing dies with 5,000 10,000 copper pillars on them and 50 micron to 127 micron pitch. And if you go chase the numbers around, you need co-planarity to roughly one part in 100,000 to put these down on a substrate, to heat them up, to cool them down, and then reflow the solder. The one part in 100,000 is like finding a blade of grass in the length of a football field. We bought some nice Keyence tools that we’re using in all of our facilities for measuring planarity of die and substrates. Then, of course, you’ve got the whole problem of how do you manage this warpage through the reflow cycles? It’s a problem.

Chen: I remember people talking about Ponte Vecchio, where they used low-temperature solder because of assembly, not because of operation.

SE: How does photonics fit into this, because there is still thermal dissipation from all the nearby circuitry?

Roosendaal: You need to simulate everything thermally, but you also need to do high frequency extraction because the electrical signals going in there are high frequency. So you need to look at impedance matching and correct grounding and those kind of things. Temperature gradients are huge. They can be inside the die, but also between the ‘E’ die and the ‘P’ die, as we call them, the electrical and the photonic die. And I’d be curious whether we need to know more about the thermal properties of adhesives.

SE: That leads to a discussion about bonding materials, options, and how they hold up over time. The obvious one is hybrid bonding, which has been used in the real world, but it hasn’t actually been used in volume manufacturing. Where are we with that?

Kelly: Everyone in the supply chain is looking at it. It’s a foundry play today, but the OSATs are looking seriously at what is the business case where it could make sense. The classic copper hybrid dielectric bonded part is is tried and true. If you can manage the cleanliness, the process will yield a part that is pretty robust. But it requires extreme cleanliness, and the capital equipment set needed to get into that is expensive. We had this early surge with AMD parts in their Ryzen line with big chunks of SRAM being copper hybrid bonded. But I have not seen a lot of traction from other customers. It’s on their road maps, but it feels like it’s a few more years out to when the equipment set can have self-contained cleanliness. If you can put it in a relatively dirtier factory than a fab, and hopefully a lower-cost environment, then maybe this will get more traction.

Chen: At ECTC 2024 there were at least, by my count, 37 papers on hybrid bonding. It’s a process that requires a lot of knowledge, but also a lot of tender loving care on the assembly process. So it will come. There are a few applications today, but it will happen for everybody.

SE: And by ‘tender loving care’ do you mean lots of money?

Chen: Time and knowledge, for sure. And you need a very clean room to do it in. That costs money. It needs equipment. That costs money, too. So it’s not just the operation. It’s just the investment in the facilities.

SE: Do you anticipate micro-bumps will be extended further than people expected, because that’s where the installed base is?

Kelly: Yes. At 15-micron pitch or higher, there’s a lot of interest in just doing copper pillar die-to-wafer. It’s kind of an idealized situation where the wafers are bone flat, the die aren’t very large, and you can still do mass reflow down to some of those pitches. It’s a little bit tricky, but it’s a lot lower cost than having to go commit to copper hybrid. But if you’re at 10 microns or below, it’s different. These guys with the stacks are going to single-digit pitches — 4 or 5 microns — and there’s no other way to get this accomplished. So it’s going to come. But the incumbent technology is always improving a little bit too. So now we’re seeing how far can we extend copper pillar and whether that last long enough that so the customer can put off all the design and the ‘qual’ development investments for going to true copper hybrid.

Chen: We will only do it only when we need to do it.

SE: We’ve seen this with thermal interface materials, right? You only use them when necessary because they’re expensive.

Kelly: Yes, only when it’s absolutely required.

SE: Is there a lot happening in epoxy molding compounds these days?

Kelly: Mold compounds have changed a lot. The CTE has gotten a lot lower, so it’s more friendly from a stress standpoint.

Otte: Going back to what we’ve discussed, what fraction of the semiconductor die today are being built using these 1 or 2 micron pitches?

Kelly: It’s a pretty small fraction.

Chen: Maybe less than 1%.

Otte: So we’re talking about technologies that are not close to mainstream. That’s not research level, because the leading edge people are really doing it, but it’s expensive and low-volume.

Kelly: It’s high-performance compute. It’s here today, and that doesn’t mean just data centers. It’s also high-end PCs and even some hand-held devices that are they’re relatively smaller, but which are still high-performance. If you look across the world of applications for processors, and just CMOS, it’s still a relatively small fraction. The meat and potatoes chipmakers don’t need to do this.

Otte: That’s why it’s surprising to see the degree to which they’re going into automotive. Automotive doesn’t have the demand for small physical sizes. They could stay with 20 or 40 nanometer sizes, because that’s where the lowest cost-per-transistor is in semiconductors.

Kelly: But the compute requirements for ADAS or autonomous driving are the same as for an AI PC or something like that. So they do need to invest in those leading-edge technologies.

SE: And they also don’t want to be left behind, right? If they have five-year cycles, maybe they can get another five years out of it.

Kelly: That’s a good point. There’s another angle for the automotive guys, too. Just imagine the part numbers they have to deal with for simple servo-controllers or fairly straightforward analog devices that work just great. Those have been around for 20 years and they’re really low cost. They’re small die. The automotive guys want to stick with them. They only want to invest in a digital chiplet for a very high-end compute piece, and maybe surround that with low-cost analog, flash, and RF. For them, the chiplet model makes a lot of sense because they can keep a lot of their older-generation parts that are low cost and working just fine. They don’t want to change them and they don’t need to. And then they just add a high-end 5 or 3nm chiplet to get the ADAS piece done. They’re really throwing a lot of different kinds of chiplets into a single product. Unlike the PC and the compute world, there is a lot more variety.

Chen: And they don’t have to be next to the engine, so it’s a good environment.

SE: Except in places like Phoenix, right?

Kelly: Yes, and the ambient temperatures for auto are high. So even if they’re not terribly high power, they have to spend some money on a good thermal solution, even contemplating things like indium TIMs because their ambient situation is so demanding.