Blog Review: Dec. 11

Synopsys’ Brent Gregory has developed a career growth checklist for computer science majors. They should hang this in the hallway at universities.

Cadence’s Brian Fuller interviews Saar Drimer, a UK hardware engineer who has been experimenting with odd-shaped PCBs. According to Drimer, 45-degree angles aren’t always optimal. But what happens to all the expensive tools everyone has been buying?

Mentor’s Colin Walls digs into diagnostic logic and trace and its role in automotive infotainment debugging. It’s clear that conference organizers in this space don’t have much of a sense of humor when it comes to paper titles.

Real Intent partner Robert Eichner adds a formal side to clock domain crossing with a video presentation about unexpected failure signature.

ARM’s Karthik Ranjan and Dominic Pajak discuss starting points for the Internet of Things and what are the key points you need to be thinking about during development. Grab some coffee. There’s a lot to absorb here.

Synopsys’ Darcy Pierce provides step-by-step instructions for using Twitter as your personal news aggregator. All you need now is time to read it all.

Cadence’s Richard Goering looks at RTL synthesis and design for test, both of which are coming into vogue at advanced process nodes. There’s a new term here, as well: giga-gate chips. Try not to break any teeth saying it.

Fist bumping is better than shaking hands during flu season. Check out the short blog from Lori Kate Smith.

And in case you missed last week’s Low Power-High Performance newsletter, here are some noteworthy blogs:

– Mentor Graphics’ Christen Decoin contends that for advanced nodes, effective power grid analysis is critical to ensure interconnects can handle current demands.

– Synopsys’ David Hsu writes that native low power simulation is inherent in today’s advanced simulation environments to understand power design intent.

– ANSYS-Apache’s Arvind Shanmugavel warns that designers need to pay close attention to interconnect reliability metrics for electromigration…or else.

– Atrenta’s Mark Baker says big power savings are available with SoC-level power exploration…and he’s not alone.

– Calypto’s Abhishek Ranjan says there are big savings, but it’s important to know which power metric is being targeted for effective optimization.

– And Nvidia’s Barry Pangrle shines a spotlight on The Green500 and the charge toward exascale computing. They’re faster, but much more energy-efficient than in the past.