Blog Review: Sept. 17
By Jesse Allen - 17 Sep, 2025 - Comments: 0

Siemens' John McMillan explores the fundamentals of IC package thermal resistance, modeling strategies, and why die-level thermal analysis in 3D-ICs is increasingly essential for ensuring device reliability. Cadence's Jasmine Makhija provides an overview of the TEE Device Interface Security Protocol (TDISP), which helps safeguard PCIe devices within Trusted Execution Environments by providin... » read more

Performance And Energy Characterization Of A Commercial Compute-in-SRAM Device (Cornell, USC, MIT, GSI)
By Technical Paper Link - 16 Sep, 2025 - Comments: 0

A new technical paper titled "Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device" was published by researchers at Cornell University, USC, MIT and GSI Technology Inc. Abstract "Compute-in-SRAM architectures offer a promising approach to achieving higher performance and energy efficiency across a range of data-intensive applications. However, prior evalu... » read more

Chip Industry Technical Paper Roundup: Sept 16
By Emma Riverso - 16 Sep, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=477 /] Find more semiconductor research papers here. » read more

Cost-Effective, Orthogonal Approach to Resilient Memory Design (Univ. of Central Florida, UT San Antonio, Rochester)
By Technical Paper Link - 16 Sep, 2025 - Comments: 0

A new technical paper titled "SCREME: A Scalable Framework for Resilient Memory Design" was published by researchers at University of Central Florida, University of Texas at San Antonio and University of Rochester. Abstract "The continuing advancement of memory technology has not only fueled a surge in performance, but also substantially exacerbate reliability challenges. Traditional soluti... » read more

Research Bits: Sept. 16
By Jesse Allen - 16 Sep, 2025 - Comments: 0

Beyond-EUV resists Researchers from Johns Hopkins University, East China University of Science and Technology, École Polytechnique Fédérale de Lausanne (EPFL), Soochow University, Brookhaven National Laboratory, and Lawrence Berkeley National Laboratory propose a combination of new resist materials and a higher-powered EUV process that could enable smaller chip feature sizes. The "beyond... » read more

HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.)
By Technical Paper Link - 16 Sep, 2025 - Comments: 0

A new technical paper titled "Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions" was published by researchers at Tampere University. Abstract "Custom instruction (CI) set extensions are beneficial for increasing performance and energy efficiency in a set of target applications. For rapid prototyping of these types of application-specific processors, desig... » read more

KAN Acceleration: Algorithm Hardware Co-Design Approach (Georgia Tech, National Tsing Hua Univ., TSMC)
By Technical Paper Link - 16 Sep, 2025 - Comments: 0

A new technical paper titled "Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems" was published by researchers at Georgia Institute of Technology, National Tsing Hua University and TSMC. Abstract "Recent developments have introduced Kolmogorov-Arnold Networks (KAN), an innovative architectural paradigm capable of replicating conventional deep neural network (DNN... » read more

HW-SW Co-Designed System With 3 Core Optimization Pathways For Long-Context Agentic LLM Inference (Cambridge, ICL)
By Technical Paper Link - 15 Sep, 2025 - Comments: 0

A new technical paper titled "Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference" was published by researchers at University of Cambridge, Imperial College London and University of Edinburgh. Abstract "LLMs now form the backbone of AI agents for a diverse array of applications, including tool use, command-line agents, and web or computer use agents. The... » read more

Identifying Divergences in HW Designs For High Performance Computing Workloads (LBNL et al.)
By Technical Paper Link - 15 Sep, 2025 - Comments: 0

A new technical paper titled "Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads" was published by Lawrence Berkeley National Lab (LBNL), Foundation for Research and Technology - Hellas and University of Houston Clear Lake. Abstract "Developing efficient hardware accelerators for mathematical kernels used in scientific applications and machine learning has tra... » read more

Analog IMC Attention Mechanism For Fast And Energy-Efficient LLMs (FZJ, RWTH Aachen)
By Technical Paper Link - 15 Sep, 2025 - Comments: 0

A new technical paper titled "Analog in-memory computing attention mechanism for fast and energy-efficient large language models" was published by researchers at Forschungszentrum Jülich and RWTH Aachen. Abstract "Transformer networks, driven by self-attention, are central to large language models. In generative transformers, self-attention uses cache memory to store token projec... » read more

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