Chip Industry Technical Paper Roundup: July 15


New technical papers recently added to Semiconductor Engineering’s library: [table id=446 /] Find more semiconductor research papers here. » read more

Three Methods For Improving Planarization For Diverse Layouts In Advanced Nodes (Fraunhofer IPMS)


A new technical paper titled "Reduced Topography After Stop on Nitride (SON) STI CMP Through Improved Post-Bulk Planarity for Diverse Layouts in Advanced Nodes" was published by researchers at Fraunhofer IPMS. Abstract "Three methods for improving planarization in a ceria free, two step STI CMP process were investigated using patterned test wafers representing 2X nm technology. It was found... » read more

Photonic SRAM Facilitating Electro-Optic Data Storage For Ultra-Fast IMC (UW-Madison, USC)


A new technical paper titled "X-pSRAM: A Photonic SRAM with Embedded XOR Logic for Ultra-Fast In-Memory Computing" was published by researchers at University of Wisconsin–Madison and USC. Abstract "Traditional von Neumann architectures suffer from fundamental bottlenecks due to continuous data movement between memory and processing units, a challenge that worsens with technology scaling ... » read more

Co-Designing Data Center Architecture To Support LLMs (Intel, Georgia Tech)


A new technical paper titled "Scaling Intelligence: Designing Data Centers for Next-Gen Language Models" was published by Intel Corporation and Georgia Tech. An excerpt from the paper's abstract: "Our work provides a comprehensive co-design framework that jointly explores FLOPS, HBM bandwidth and capacity, multiple network topologies (two-tier vs. FullFlat optical), the size of the scale-ou... » read more

GAA Transistors: 3D Atomic-Scale Metrology of Strain Relaxation and Roughness via Electron Ptychography (Cornell, ASM, TSMC)


A new technical paper titled "3D Atomic-Scale Metrology of Strain Relaxation and Roughness in Gate-All-Around (GAA) Transistors via Electron Ptychography" was published by researchers at Cornell University, ASM and TSMC. Abstract "To improve transistor density and electronic performance, next-generation semiconductor devices are adopting three-dimensional architectures and feature sizes dow... » read more

Data Center CPU Dominance Is Shifting To AMD And Arm


Fig. 1: Created by ChatGPT from a text prompt. The data center processor market has seen two major tectonic shifts in the last decade. It used to be that all data center compute was x86, and well more than 90% of that was Intel. GPUs first appeared in the data center in 2016 (Pascal GPU). Now, the majority of computation is done on GPUs. AMD is looking to pass Intel in x86 share, and... » read more

Startup Funding: Q2 2025


Investors were drawn to a wide range of innovative approaches in Q2 2025, backing startups developing superconducting logic, chips for an emerging number format, big data processors, and novel power semi architectures. At the same time, photonics continues to draw investment dollars due to its ability to move data faster and with less energy at both the chip-to-chip and data center levels. T... » read more

Colloidal Coordination Nanosheets, And Their Use as Inks For Coating (Tokyo University of Science)


A new technical paper titled "Rationally Engineered Heterometallic Metalladithiolene Coordination Nanosheets with Defined Atomic Arrangements" was published by researchers at Tokyo University of Science. Abstract "Coordination nanosheets are 2D polymers formed by coordination bonds between metal ions and planar organic molecules. They offer high molecular design freedom and unique electroni... » read more

Chip Industry Week In Review


GlobalFoundries plans to acquire MIPS, adding RISC-V processor IP and PPA optimization software capabilities to its foundry offerings. MIPS will continue to operate as a standalone business within GF. The deal is expected to close in the second half of 2025. The EU rolled out new general-purpose AI rules this week to limit copyright infringement, protect public safety, and require transparency... » read more

Using Picosecond Ultrasonic Technology For AI Packages: Part 2


Heterogeneous integration is a key enabler of today’s AI innovations. By bringing together multiple chips with different functionalities, a.k.a., chiplets, AI devices have been able to achieve tremendous performance gains. However, the heterogeneous integration of advanced packages has its own set of process control obstacles that must be addressed, including new interconnect challenges invol... » read more

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