Blog Review: July 16


Synopsys' Bradley Geden and Manoz Palaparthi explain the difference between functional signoff and RTL signoff and why increased SoC complexity means that verification flows must now capture both the intent and the integrity of a design before it can move forward. Cadence's Frank Ferro finds that LPDDR isn't just for mobile devices anymore, with the new LPDDR6 standard bringing increased ban... » read more

Semiconductor Value Chain With A Focus On IP Providers


By Global Semiconductor Alliance (GSA) The semiconductor industry operates within a complex and rapidly evolving ecosystem driven by continuous innovation. Central to this ecosystem is the semiconductor value chain, which includes several key stages: chip design, wafer fabrication, final assembly, and raw material sourcing. Each stage is crucial to the production and functionality of semicon... » read more

Volatile And Non-Volatile NEM Switches Fabricated In A CMOS-Compatible SOI Foundry Platform (KTH, U. of Bristol, EPFL, Imec)


A new technical paper titled "Volatile and non-volatile nano-electromechanical switches fabricated in a CMOS-compatible silicon-on-insulator foundry process" was published by researchers at KTH Royal Institute of Technology, University of Bristol, EPFL, imec, and Ghent University. Abstract "Nanoelectromechanical (NEM) switches have the advantages of zero leakage current, abrupt switching ch... » read more

Report: The AI Efficiency Boom


Artificial Intelligence (AI) is undergoing a fundamental transformation. While early AI models were large, compute-heavy, and dependent on cloud processing, a new wave of efficiency-driven innovations is moving AI inference—the generation of model results—to the edge. Smaller models, improved memory and compute performance, and the need for privacy, low latency, and energy efficiency are dr... » read more

AI In Chip Design: Tight Control Required


Executive Outlook: Semiconductor Engineering sat down with a panel of experts to talk about what's needed to effectively leverage AI, who benefits from it, and where software-defined hardware works best, with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Ze... » read more

Expanding Server Memory Capabilities With Multiplexed Rank DIMM (MRDIMM) Technology


The scaling of computational power within a single, packaged semiconductor component continues to rise following a Moore’s law type curve enabling new and more capable applications including machine learning (ML), generative artificial intelligence (AI), and training and deployment of large language models (LLM). On-demand lifestyle applications like language translation, direction finding, a... » read more

Physics-Based ASICs (Normal Computing et al.)


A new technical paper titled "Solving the compute crisis with physics-based ASICs" was published by researchers at Normal Computing Corporation, ARIA, UC Santa Barbara, University of Pennsylvania, Santa Fe Institute, Cornell University. Advanced Research Projects Agency - Energy and Yale University. Abstract "Escalating artificial intelligence (AI) demands expose a critical "compute crisis"... » read more

Silicon IP Revenue Spikes


EDA and silicon IP revenue grew 12.8% in Q1 2025, totaling $5.098 billion compared to $4.522 billion in the same period last year, but the real story was on the IP side, surging 29.6% year-over-year to $1.577 billion. Drilling deeper into those numbers, revenue for non-reporting IP companies — predominantly Arm — jumped 34.1% YoY to $1.031 billion. That was positive news for the IP marke... » read more

Cognichip: Using AI To Speed Complex Chip Design


AI software innovation is accelerating, while the chip design process is struggling to keep pace due to rising complexity and physical constraints. The big challenge now is how to close that gap. The solution is at least as complex as the hardware design. It requires much greater reuse of IP, along with portions of existing designs, so that not everything needs to be created from scratch. AI... » read more

Analysis of RISC-V CPU Fuzzers via Automatic Bug Injection (ETH Zurich)


A new technical paper titled "Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection" was published by researchers at ETH Zurich. Abstract "Hardware fuzzing has recently gained momentum with many discovered bugs in open-source RISC-V CPU designs. Comparing the effectiveness of different hardware fuzzers, however, remains a challenge: each fuzzer optimizes for a different metric and ... » read more

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