Programmable Hardware Delivers 10,000X Improvement In Verification Speed Over Software For Forward Error Correction


In the race to increase the speeds of wireline networking and communications, forward error correction (FEC) has become a vital part of the toolkit. To function effectively, especially with the increasing use of four-level pulse amplitude modulation (PAM4), high-speed protocols need FEC to avoid a rise in the number of reception errors. Each incremental increase in the transmitted symbol rate r... » read more

Security Vulnerabilities Difficult To Detect In Verification Flow


As designs grow in complexity and size, the landscape for potential hackers to infiltrate a chip at any point in either the design or verification flow increases commensurately. Long considered to be a “safe” aspect of the design process, verification now must be a focus of chip developers from a security perspective. This also means the concept of trust has never been higher, and the tr... » read more

Disruptive Changes Ahead For Photomasks?


Experts at the Table: Semiconductor Engineering sat down with four experts to explore the current state and future direction of mask-making, with insights from Harry Levinson, principal lithographer at HJL Lithography; Aki Fujimura, CEO of D2S; Ezequiel Russell, senior director of mask technology at Micron; and Christopher Progler, executive vice president and CTO at Photronics. What follows ... » read more

3D Packaging vs 3D Integration eBook


In this eBook, you will: •    Explore the background and trends of multi-die packages •    Learn about the distinct approaches of 3D packaging and 3D integration •    Examine the challenges within heterogeneous integration Read more here. » read more

HW Security: Multi-Agent AI Assistant Leveraging LLMs To Automate Key Stages of SoC Security Verification (U. of Florida)


A new technical paper titled "SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models" was published by researchers at University of Florida. Abstract "Ensuring the security of complex system-on-chips (SoCs) designs is a critical imperative, yet traditional verification techniques struggle to keep pace due to significant challenges in automation, scalability, c... » read more

Blog Review: June 25


Siemens’ John McMillan provides a detailed overview of 3D-IC technology and heterogeneous integration, from the market trends driving its adoption to the design, verification, and manufacturing challenges involved. Synopsys’ Gunnar Braun and Stewart Williams check out how cloud-based development practices and virtual prototypes can enable earlier and more efficient testing and validation... » read more

Design and Test Solutions for E-Mobility and Autonomous Driving


The automotive industry is accelerating its electronic technology revolution and fusing with the clean energy ecosystem. By 2030, 4.2 million cars will be autonomous and 50% will be electric. Dramatic increases in the number of sensors and applications in new automobiles have evolved the vehicle from a peripheral role to a network hosting clusters of connected devices. Cars now need to be o... » read more

Device Architecture For 2D Material-Based mNS-FETs In Sub-1nm Nodes (Sungkyunkwan Univ., Alsemy)


A new technical paper titled "Exploring optimal TMDC multi-channel GAA-FET architectures at sub-1nm nodes" was published by researchers at Sungkyunkwan University and Alsemy Inc. "This paper explores the design and optimization of multi-Nanosheet Field-Effect Transistors (mNS-FETs) employing a Transition Metal Dichalcogenide (TMDC) channel, specifically MoS2, for the 0.7 nm technology node u... » read more

Wafer Bonding Mechanisms Using SiCN Films For Hybrid Bonding Applications In 3D Integration 


A new technical paper titled "Material-Mechanistic Interplay in SiCN Wafer Bonding for 3D Integration" was published by researchers at Yokohama National University, TEL, SK hynix, and University of Tsukuba. According to the paper: "Although much research has been conducted on wafer bonding methods compatible with the latest semiconductor manufacturing processes, discussions on the interface... » read more

Platform for LN-Based Wavelength-Scale Integrated Phononic Waveguides On Diamond (Stanford, UCSB)


A new technical paper titled "Integrated phononic waveguide on thin-film lithium niobate on diamond" was published by researchers at Stanford University and UC Santa Barbara. Abstract "We demonstrate wavelength-scale phononic waveguides formed by transfer-printed thin-film lithium niobate (LN) on bulk diamond (LNOD), a material stack that combines the strong piezoelectricity of LN with the ... » read more

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