Co-Packaged Optics To Train/Run GenAI Models in Data Centers (IBM)


A new technical paper titled "Next generation Co-Packaged Optics Technology to Train & Run Generative AI Models in Data Centers and Other Computing Applications" was published by researchers at IBM. Abstract "We report on the successful design and fabrication of optical modules using a 50 micron pitch polymer waveguide interface, integrated for low loss, high density optical data transf... » read more

Ammonia Plasma Surface Treatment for Improved Cu–Cu Bonding Reliability


A new technical paper titled "Ammonia Plasma Surface Treatment for Enhanced Cu–Cu Bonding Reliability for Advanced Packaging Interconnection" was published by researchers at Myongji University. Abstract "With the emergence of 3D stacked semiconductor products, such as high-bandwidth memory, bonding-interface reliability cannot be overemphasized. The condition of the surface interface befo... » read more

Wafer Bin Map Defect Classification Using Semi-Supervised Learning


A new technical paper titled "Semi-Supervised Learning with Wafer-Specific Augmentations for Wafer Defect Classification" was published by researchers at Korea University. Abstract "Semi-supervised learning (SSL) models, which leverage both labeled and unlabeled datasets, have been increasingly applied to classify wafer bin map patterns in semiconductor manufacturing. These models typical... » read more

Research Bits: Dec. 24


Growing multilayered chips Researchers from MIT, Samsung Advanced Institute of Technology, Sungkyunkwan University, and University of Texas at Dallas developed a method to fabricate a multilayered chip with alternating layers of semiconducting material grown directly on top of each other. The approach enables high-performance transistors and memory and logic elements on any random crystalline ... » read more

Semiconductor Engineering’s Special Reports 2024


Semiconductor Engineering published 36 special reports in 2024. Focus Areas Manufacturing, Packaging, Materials Test, Measurement New Fabs and Funding Memory Design Power, Performance Manufacturing, Packaging, Materials Navigating Increased Complexity In Advanced Packaging  Intel Vs. Samsung Vs. TSMC Hybrid Bonding Makes Strides Toward Manufacturability 3.5D: The Great Comp... » read more

Chip Industry Technical Paper Roundup: Dec. 23


New technical papers recently added to Semiconductor Engineering’s library: [table id=394 /] Find all technical papers here. » read more

CXL’s Potential to Elevate The Capabilities of HPC and AI Applications (Micron, Intel)


A new technical paper titled "Optimizing System Memory Bandwidth with Micron CXL Memory Expansion Modules on Intel Xeon 6 Processors" was published by researchers at Micron and Intel. Abstract "High-Performance Computing (HPC) and Artificial Intelligence (AI) workloads typically demand substantial memory bandwidth and, to a degree, memory capacity. CXL memory expansion modules, also known... » read more

Fully Partitioned Security Monitoring Logic From Both The CPU’s Main Core and Privileged SW (KAIST)


A new technical paper titled "Interstellar: Fully Partitioned and Efficient Security Monitoring Hardware Near a Processor Core for Protecting Systems against Attacks on Privileged Software" was published by researchers at KAIST. The paper states "The existing approaches to instruction trace-based security monitoring hardware are dependent on the privileged software, which presents a signific... » read more

Chip Industry Week In Review


Updated for 12/20 government fundings and 12/23 for China trade investigation announcements. President Biden announced a trade investigation into "China's unfair trade practices in the semiconductor sector."  The announcement stated "PRC semiconductors often enter the U.S. market as a component of finished goods. This Section 301 investigation will examine a broad range of the PRC’s non-m... » read more

Accelerating Artificial Intelligence Innovation With Concurrent Design Engineering


Artificial intelligence (AI) is transforming every industry and creating new demands for computing performance, efficiency, and scalability. Designers are creating and deploying AI-dedicated chips to meet these challenges and enable faster and smarter applications across various domains, such as cloud, edge, mobile, automotive, and the Internet of Things (IoT). However, designing AI chips is no... » read more

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