Conquer Placement And Clock Tree Challenges In HPC Designs


High-performance computing (HPC) applications require IC designs with maximum performance. However, as process technology advances, achieving high performance has become increasingly challenging. Designers need digital implementation tools and methodologies that can solve the thorny issues in HPC designs, including placement and clock tree challenges. Placement and clock tree synthesis are c... » read more

Server Design With Pin-Efficient CXL Interface (Georgia Tech)


A new technical paper titled "A Case for CXL-Centric Server Processors" was written by researchers at Georgia Tech. Abstract: "The memory system is a major performance determinant for server processors. Ever-growing core counts and datasets demand higher bandwidth and capacity as well as lower latency from the memory system. To keep up with growing demands, DDR--the dominant processor inter... » read more

Quantum: Loophole-​Free Bell Test with Superconducting Circuits (ETH Zurich)


A new technical paper titled "Loophole-free Bell inequality violation with superconducting circuits" was published by a group of researchers led by ETH Zurich. Abstract (partial) "Here we demonstrate a loophole-free violation of Bell’s inequality with superconducting circuits, which are a prime contender for realizing quantum computing technology. To evaluate a Clauser–Horne–Shimony... » read more

Placement And CTS Techniques For High-Performance Computing Designs


This paper discusses the challenges of designing high-performance computing (HPC) integrated circuits (ICs) to achieve maximum performance. The design process for HPC ICs has become more complex with each new process technology, requiring new architectures and transistors. We highlight how the Siemens Aprisa digital implementation solution can solve placement and clock tree challenges in HPC de... » read more

Engineering Simulation Workloads And The Rise of the Cloud


Cloud service providers (CSPs) continue to improve the performance capabilities of their non-accelerated and accelerated compute instances, as well as augment their HPC infrastructure with domain-area expertise of targeted HPC workloads. Additionally, engineers, researchers, and scientists are becoming more comfortable with the types of workloads that can be run in the cloud within acceptable w... » read more

Blog Review: May 10


Synopsys' Alessandra Nardi and Uyen Tran explain how to meet quality, reliability, functional safety, and security requirements of automotive chips through thorough test programs, path-margin monitoring, and design failure mode and effect analysis (DFMEA). Cadence's Veena Parthan explores how computational fluid dynamics can help predict and model the generation, propagation, and mitigation ... » read more

Research Bits: May 10


Growing 2D TMDs on chips Researchers from Massachusetts Institute of Technology (MIT), Oak Ridge National Laboratory, and Ericsson Research found a way to “grow” layers of 2D transition metal dichalcogenide (TMD) materials directly on top of a fully fabricated silicon chip, a technique they say could enable denser integrations. The researchers focused on molybdenum disulfide, which is f... » read more

Achieving Your Low Power Goals With Synopsys Ultra Low Leakage IO


The demand for low power design has intensified with shrinking geometries. At the same time, innovation in battery operated, handheld devices has increased the design complexity by adding more and more functionality. The focus is on power-optimized designs while maintaining low cost and reduced risk. Designers face these complex and contradictory challenges: developing products with the lowest ... » read more

Designing Crash-Proof Autonomous Vehicles


Autonomous vehicles keep crashing into things, even though ADAS technology promises to make driving safer because machines can think and react faster than human drivers. Humans rely on seeing and hearing to assess driving conditions. When drivers detect objects in front of the vehicle, the automatic reaction is to slam on the brakes or swerve to avoid them. Quite often drivers cannot react q... » read more

Performance Of Analog In-Memory Computing On Imaging Problems


A technical paper titled "Accelerating AI Using Next-Generation Hardware: Possibilities and Challenges With Analog In-Memory Computing" was published by researchers at Lund University and Ericsson Research. Abstract "Future generations of computing systems need to continue increasing processing speed and energy efficiency in order to meet the growing workload requirements under stringent en... » read more

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