AI For Data Management
By Adam Kovac - 30 May, 2024 - Comments: 0

Data management is becoming a significant new challenge for the chip industry, as well as a brand new opportunity, as the amount of data collected at every step of design through manufacturing continues to grow. Exacerbating the problem is the rising complexity of designs, many of which are highly customized and domain-specific at the leading edge, as well as increasing demands for reliabili... » read more

Embracing The Future: 5G NTN – Satellite Service For The Masses
By Allison Freedman - 30 May, 2024 - Comments: 0

In a world where communication is paramount, access to reliable networks is not just a luxury but a necessity. Traditionally, satellite communications have been reserved for specialized terminals with cumbersome antennas and costly subscription plans. However, with the advent of 5G Non-Terrestrial Networks (NTNs), the landscape of satellite phone availability is undergoing a revolutionary tran... » read more

AI Accelerated Migration Of Existing Designs To New Processors
By Rob van Blommestein - 30 May, 2024 - Comments: 0

In this fast-paced digital age where speed, performance, and time-to-market are king, chip designers are under pressure to deliver high-performance computing that doesn’t compromise power efficiency. The constant demand for instantaneous data processing and sharing is pushing the boundaries of innovation in chip design. With this context, we revisit and revamp the insights from the Synopsys U... » read more

Trouble Ahead For IC Verification
By Brian Bailey - 30 May, 2024 - Comments: 0

Verification complexity is roughly the square of design complexity, but until recently verification success rates have remained fairly consistent. That's beginning to change. There are troubling signs that verification is collapsing under the load. The first-time success rate fell (see figure 1) in the last survey conducted by Wilson Research, on behalf of Siemens EDA, in 2022. A new survey ... » read more

Physics-Based Digital Twin of a Thermally Aged Flip-Chip Package (TU Delft, NXP)
By Technical Paper Link - 29 May, 2024 - Comments: 0

A technical paper titled “Modelling thermomechanical degradation of moulded electronic packages using physics-based digital twin” was published by researchers at Delft University of Technology and NXP Semiconductors. Abstract: "Semiconductor devices are commonly encapsulated with Epoxy-based Moulding Compounds (EMC) to form an electronic package. EMC typically occupies a large volume with... » read more

Properties of Commercially Available Hexagonal Boron Nitride Grown By The CVD Method
By Technical Paper Link - 29 May, 2024 - Comments: 0

A new technical paper titled "On the quality of commercial chemical vapour deposited hexagonal boron nitride" was published by researchers at KAUST and the National Institute for Materials Science in Japan. Abstract "The semiconductors industry has put its eyes on two-dimensional (2D) materials produced by chemical vapour deposition (CVD) because they can be grown at the wafer level with sm... » read more

A Unified Solution for End-to-End Low Power Verification
By Synopsys - 29 May, 2024 - Comments: 0

Low power designs are becoming increasingly prevalent in modern electronic systems, driven by the need for energy-efficient devices. Ensuring the correctness of these designs is paramount, as even minor errors can lead to catastrophic consequences. To achieve verification closure for low power designs, a combination of static verification, dynamic simulation-based verification, formal verificat... » read more

Will Chiplet Adoption Mimic IP Adoption?
By Alphawave Semi - 29 May, 2024 - Comments: 0

If we look at the semiconductor industry expansion during the last 25 years, adoption of design IP in every application appears to be one of the major factors of success, with silicon technology incredible development by a x100 factor, from 250nm in 2018 to 3nm (if not 2nm) in 2023. We foresee the move to chiplet-based architecture to soon play the same role that SoC chip-based architecture and... » read more

Distribution of Currents In Via Arrays
By Siemens EDA - 29 May, 2024 - Comments: 0

It has become increasingly difficult in recent years to provide adequate PDNs on a PCB. The sheer number of different voltages, combined with increased current demands, makes distributing current around the board a substantial layout challenge. This paper demonstrates that by using appropriate and accurate simulations, combined with the improved intuition that such simulations bring, it is a ch... » read more

Considerations to Successfully Integrate Chiplets in Designs
By Keysight - 29 May, 2024 - Comments: 0

Chiplet integration is a promising approach to creating heterogeneous and complex system-on-chips (SoCs) with significant performance, power, scalability, flexibility, and cost benefits. However, chiplet integration also poses substantial design, verification, testing, and packaging challenges, requiring new standards and design methodologies. Electronic design automation (EDA) software and sim... » read more

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