Energy-Efficient SoCs For The Zettabyte Era Using Power-Saving IP And System Design Techniques
By Cadence - 10 Nov, 2021 - Comments: 0

As the modern world becomes increasingly connected, businesses and consumers alike are relying more and more on digital data. Behind the scenes, data centers that manage all of this digital data are a somewhat silent, yet impactful, part of this connectivity revolution. These data centers are lined with servers that process digital data for everything from social media status updates to analyti... » read more

HBM2E Raises The Bar For Memory Bandwidth
By Rambus - 10 Nov, 2021 - Comments: 0

AI/ML training capabilities are growing at a rate of 10X per year driving rapid improvements in every aspect of computing hardware and software. HBM2E memory is the ideal solution for the high bandwidth requirements of AI/ML training, but entails additional design considerations given its 2.5D architecture. Designers can realize the full benefits of HBM2E memory with the silicon-proven memory s... » read more

PPA(V): Performance-Per-Watt Optimization With Variable Operating Voltage
By Synopsys - 10 Nov, 2021 - Comments: 0

Performance-per-watt has emerged as one of the highest priorities in design quality, leading to a shift in technology focus and design power optimization methodologies. Variable operating voltage possess high potential in optimizing performance-per-watt results but requires a signoff accurate and efficient methodology to explore. Synopsys Fusion Design Platform, uniquely built on a singular RTL... » read more

Autoencoder-Based Characterisation Of Passive IEEE 802.11 Link Level Measurements
By Fraunhofer IIS/EAS - 10 Nov, 2021 - Comments: 0

Wireless networks are indispensable in today’s industrial manufacturing and automation. Due to harsh signal propagation conditions as well as co-existing wireless networks, transmission failures resulting in severe application malfunctions are often difficult to diagnose. Remote wireless monitoring systems are extremely useful tools for troubleshooting such failures.However, the completeness ... » read more

Bandwidth Utilization Side-Channel On ML Inference Accelerators
By Arm - 10 Nov, 2021 - Comments: 0

Abstract—Accelerators used for machine learning (ML) inference provide great performance benefits over CPUs. Securing confidential model in inference against off-chip side-channel attacks is critical in harnessing the performance advantage in practice. Data and memory address encryption has been recently proposed to defend against off-chip attacks. In this paper, we demonstrate that bandwidth... » read more

Debugging Embedded Applications
By Ann Mutschler - 10 Nov, 2021 - Comments: 0

Debugging embedded designs is becoming increasingly difficult as the number of observed and possible interactions between hardware and software continue to grow, and as more features are crammed into chips, packages, and systems. But there also appear to be some advances on this front, involving a mix of techniques, including hardware trace, scan chain-based debug, along with better simulation ... » read more

Failure Modes Of Wearable Electronics
By Ansys - 10 Nov, 2021 - Comments: 0

Society has been enamored with wearable electronics for many years. From FitBit to Google Glass to Apple Watch, taking electronic technology to the next level has fascinated us. Wiki defines wearable computers (also known as body-borne computers or wearables) as miniature electronic devices that are worn by the bearer under, with or on top of clothing. This class of wearable technology has been... » read more

Blog Review: Nov. 10
By Jesse Allen - 10 Nov, 2021 - Comments: 0

Cadence's Paul McLellan listens in as Malcolm Penn of Future Horizons explains key reasons behind the cyclical nature of the semiconductor industry and how the root of the current chip shortage problems goes back to before the pandemic. Siemens EDA's Ray Salemi continues investigating using Python for verification with a look at some UVM utilities and how they would be used in Python. Syn... » read more

HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment
By Technical Paper Link - 09 Nov, 2021 - Comments: 0

Summary "To ensure secure and trustworthy execution of applications, vendors frequently embed trusted execution environments into their systems. Here, applications are protected from adversaries, including a malicious operating system. TEEs are usually built by integrating protection mechanisms directly into the processor or by using dedicated external secure elements. However, both of these... » read more

A graph placement methodology for fast chip design
By Technical Paper Link - 09 Nov, 2021 - Comments: 0

Abstract "Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research1, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method autom... » read more

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