Defect Mitigation And Characterization In Silicon Hardmask Materials
By Brewer Science - 17 Mar, 2021 - Comments: 0

From SPIE Digital Library: In this study, metal contaminants, liquid particle count and on-wafer defects of Si- HMs and filtration removal rates are monitored to determine the effect of filter type, pore size, media morphology, and cleanliness on filtration performance. 5-nm PTFE NTD2 filter having proprietary surface treatment used in this study shows lowest defect count. Authors: Vineet... » read more

Chip Board Interaction Analysis Of 22nm FD-SOI Technology In WLP
By Amkor - 17 Mar, 2021 - Comments: 0

Recently, Wafer Level Packaging (WLP) has been in high demand, especially in mobile device applications as a path to enable miniaturization while maintaining good electrical performance. The relatively inexpensive package cost and simplified supply chain are encouraging other industries to adapt WLP capabilities for radio frequency (RF), communications/sensing (mmWave) and automotive applicatio... » read more

Hunting For Open Defects In Advanced Packages
By Anne Meixner - 17 Mar, 2021 - Comments: 5

Catching all defects in chip packaging is becoming more difficult, requiring a mix of electrical tests, metrology screening, and various types of inspection. And the more critical the application for these chips, the greater the effort and the cost. Latent open defects continue to be the bane of test, quality, and reliability engineering. Open defects in packages occur at the chip-to-substra... » read more

Blog Review: March 17
By Jesse Allen - 17 Mar, 2021 - Comments: 0

Synopsys' Chris Clark considers the growing number of automotive sensors and the cost/performance tradeoffs between edge computing capability, sensor fusion, sensor degradation, monitoring, and the maintenance of the software over the lifespan of a vehicle. Cadence's Paul McLellan checks out how the process of loading the bootstrap into memory has changed over the years, from hand-entered on... » read more

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing
By eBeam Initiative - 17 Mar, 2021 - Comments: 0

The Survey: 2021 Deep Learning Applications List by eBeam Initiative members is a list of current deep learning efforts that are being used in photomask to wafer semiconductor manufacturing. Examples come from ASML, D2S, Fraunhofer IPMS, Hitachi High-Tech Corporation, imec, Siemens Industries Software, Inc., Siemens EDA, STMicroelectronics, and TASMIT. Published by the eBeam Initiative Membe... » read more

Manufacturing Bits: March 16
By Mark LaPedus - 16 Mar, 2021 - Comments: 0

Tripping up neural networks For years, Russia has been an active area in R&D. In one example, Russia's Skolkovo Institute of Science and Technology (Skoltech) has demonstrated how certain patterns can cause neural networks to make mistakes in recognizing images. Leveraging the theory behind this research, Skoltech can design defenses for pattern recognition systems that are vulnerable t... » read more

Power/Performance Bits: March 16
By Jesse Allen - 16 Mar, 2021 - Comments: 0

Adaptable neural nets Neural networks go through two phases: training, when weights are set based on a dataset, and inference, when new information is assessed based on those weights. But researchers at MIT, Institute of Science and Technology Austria, and Vienna University of Technology propose a new type of neural network that can learn during inference and adjust its underlying equations to... » read more

The Benefits Of Curvilinear Shapes On Photomasks
By Jan Willis - 15 Mar, 2021 - Comments: 0

Do you have four minutes to hear why companies like Micron Technology think that curvilinear shapes on photomasks are an advantage? In a short video, Ezequiel Russell, Senior Director of Mask Technology at Micron Technology shows how curvilinear shapes can increase process windows for advanced memory as shown in figure 1. The video was part of a longer panel discussion with industry experts at ... » read more

Designing 2.5D Systems
By Brian Bailey - 15 Mar, 2021 - Comments: 0

As more designs hit the reticle limit, or suffer from decreasing yield, migrating to 2.5D designs may provide a path forward. But this kind of advanced packaging also comes with some additional challenges. How you adapt and change your design team may be determined by where your focus has been in the past, or what you are trying to achieve. There are business, organizational, and technical c... » read more

An Insider’s View Of Verifying Custom RISC-V Processor Cores
By Shubhodeep Roy Choudhury - 15 Mar, 2021 - Comments: 0

By Shubhodeep Roy Choudhury, Valtrix Systems, and Lee Moore, Imperas Software Supporting images courtesy of Bill McSpadden, Seagate Technology This article is derived from a talk at the RISC-V Summit in December 2020 that Bill McSpadden, principal verification engineer at Seagate Technology, gave on the challenges and experiences his team faced in the verification of two custom RISC-V proce... » read more

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