High-Level Synthesis For RISC-V
By Brian Bailey - 28 Oct, 2021 - Comments: 2

High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing custom processors without having to re-implement them every time at the register transfer level (RTL). There are two types of high-level synthesis (HLS) that need to be considered. The first is ge... » read more

Debug Solutions For Designers Accelerate Time To Verification
By Neil Hand - 28 Oct, 2021 - Comments: 0

Complexity continues to explode as designs become larger and more complicated with more functionality and more aggressive expectations. The cost of doing business as usual, for the entire design and verification team, in turn, grows exponentially, in terms of time, effort, and dollars. Fig. 1: Discovering issues later than possible requires more effort to find and fix. (Source: Wilson Rese... » read more

Intelligent Coverage Optimization: Verification Closure In Hyperdrive
By Anika Malhotra - 28 Oct, 2021 - Comments: 0

Coverage dominates every aspect of verification for today’s complex IP and chip designs. Coverage metrics provide critical feedback on what has been verified and what has not, especially when automated stimulus generation techniques are used. All modern hardware design and verification languages include constructs for functional coverage specification and support a range of structural coverag... » read more

Customize Off-The-Shelf Processor IP
By Roddy Urquhart - 28 Oct, 2021 - Comments: 0

Processor customization is one approach to optimizing a processor IP core to handle a certain workload. In some case it makes sense to design a dedicated core from scratch, but in many cases an existing core may partially meet your requirements and can be a good starting point for your optimized core. In the past some processor IP vendors, notably ARC and Tensilica, offered extensible cores ... » read more

Materials and Device Simulations for Silicon Qubit Design and Optimization
By Technical Paper Link - 27 Oct, 2021 - Comments: 0

Abstract: "Silicon-based microelectronics technology is extremely mature, yet this profoundly important material is now also poised to become a foundation for quantum information processing technologies. In this article, we review the properties of silicon that have made it the material of choice for semiconductor-based qubits with an emphasis on the role that modeling and simulation have play... » read more

Buried nanomagnet realizing high-speed/low-variability silicon spin qubits: implementable in error-correctable large-scale quantum computers
By Technical Paper Link - 27 Oct, 2021 - Comments: 0

Abstract: "We propose a buried nanomagnet (BNM) realizing highspeed/low-variability silicon spin qubit operation, inspired by buried wiring technology, for the first time. High-speed quantum-gate operation results from large slanting magnetic-field generated by the BNM disposed quite close to a spin qubit, and low-variation of fidelity thanks to the self-aligned fabrication process. Employing ... » read more

3D Printing For More Circuits
By Ann R. Thryft - 27 Oct, 2021 - Comments: 0

After several years of experimentation, and growing success in volume manufacturing for some use cases, technologies for 3D printing of electronic circuits are becoming more common. Some innovations in processes and materials are moving these technologies closer to mainstream electronics manufacturing. Christopher Tuck, professor of material science at the University of Nottingham, observed ... » read more

Microchip Sees Significant Productivity Gains In Mature-Node Custom IC Design With In-Design Signoff DRC
By Siemens EDA - 27 Oct, 2021 - Comments: 0

Microsemi pioneered the design of innovative chips that are used for multiple purposes across a variety of industries, using both mature and advanced process nodes. In mature node custom design implementation, layout designers still spend a significant amount of their valuable time fixing DRC errors—time that could be more beneficially spent ensuring their designs meet their PPA goals. By rep... » read more

Co-Packaged Optics And The Evolution Of Switch/Optical Interconnects In Data Centers
By Synopsys - 27 Oct, 2021 - Comments: 0

Driven by a need to reduce power and increase bandwidth density in data center network switches and other devices, the data networking industry is moving toward adoption of co-packaged optics (CPO). This paper provides a brief overview of the history of copper and optical interconnects, the limitations of existing interconnect solutions, and the future of co-packaged optics, including the benef... » read more

Blog Review: Oct. 27
By Jesse Allen - 27 Oct, 2021 - Comments: 0

Siemens EDA's Ray Salemi continues looking into using Python for verification by looking at how pyuvm simplifies and refactors the UVM TLM system to take advantage of the fact that Python has multiple inheritance and no typing. Cadence's Paul McLellan listens in as Larry Disenhof explains the impact that export regulations have on EDA tools and IP products and changes in a rapidly shifting l... » read more

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