Streaming Scan Network


The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. In the traditional approach to delivering scan test data to cores, each core requires a dedicated connection to chip-level pins, which doesn’t allow for much flexibility, as the dependencies betwee... » read more

No Safety Without Dependable Security In Automotive Designs


The cyber threat faced by the automotive industry reached public awareness in 2015, when a “White Hat” research team commandeered the control electronics of a target vehicle at freeway speeds. Subsequently published details of the team’s work identified several discrete weak links that were leveraged by the researchers to create the attack. The approach illustrated a concept well-known to... » read more

Getting Realistic About AI


By Olaf Enge-Rosenblatt and Andy Heinig The topic of artificial intelligence (AI) is omnipresent today, both in the news and on popular science shows. The number of possibilities for AI methods to assist people in making decisions are expanding rapidly. There are three main reasons for this: The development of new AI methods (deep learning, reinforcement learning); The continuous ... » read more

Securing Server Systems And Data At The Hardware Level


Across the global internet, there’s a growing need to secure data, not only coursing over the network, but within the servers in data centers and deployed at the edge. Interconnect technologies such as Compute Express Link (CXL) will enable future servers to be disaggregated into composable resources that can be finely matched to the requirements of varied workloads and support virtualized co... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs China has been working on compound semiconductors, such as gallium-nitride (GaN) and silicon carbide (SiC). Now, a China-backed company has taken a big step in the SiC and related markets. Chip supplier Nexperia, a subsidiary of China’s Wingtech Technology, has acquired Newport Wafer Fab (NWF), a U.K.-based manufacture of power and compound semiconductors, including Si... » read more

Week In Review: Design, Low Power


Tools Aldec extended its TySOM family of embedded prototyping boards with the introduction of TySOM-M-MPFS250, the first in a planned series to feature a Microchip PolarFire SoC FPGA MPFS250T-FCG1152 and to have dual FMC connectivity. The board contains 16Gb FPGA DDR4 x32, 16Gb MSS DDR4 x36 with ECC, eMMC, SPI Flash memory, 64 Kb EEPROM and a microSD card socket. The PolarFire SoC is a five-st... » read more

Week In Review: Auto, Security, Pervasive Computing


Pervasive computing — IoT, edge, cloud, data center, and back The IoT designer Deed designed a screenless health monitor, worn on the wrist, that uses IoT (Internet of Things) building blocks from Infineon Technologies. The Get bracelet interprets hand gestures for making payments, picking up phone calls, turning up or down audio, while it also takes health data and biometrics. The system us... » read more

ASIC/IC Verification Trends With A Focus On Factors Of Silicon Success


At long last we come to the final installment of our four-part series presenting the findings of the Wilson Research Group Functional Verification 2020 study. In this article we discuss verification trends in IC/ASIC language and library adoption, low power management, and verification effectiveness. We then take a deeper dive into two somewhat surprising phenomena revealed in the data: the ... » read more

For The Edge, It’s All About Location, Location, Location


They are centrally located, are connected to power grids and water systems, and are rapidly thinning out. And you can probably get a new cell phone case or a corn dog in the atrium. Could shopping malls become a future home for the edge? Edge computing has transformed over the last few years from being a vaguely defined concept to a fundamental part of the future data infrastructure. Band... » read more

Reducing Power Delivery Overhead


The power delivery network (PDN) is a necessary overhead that typically remains in the background — until it fails. For chip design teams, the big question is how close to the edge are they willing to push it? Or put differently, is the gain worth the pain? This question is being scrutinized in very small geometry designs, where margins can make a significant difference in device performan... » read more

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