Finding Hotspots In AI Chips
By Stephen Crosher - 14 Nov, 2019 - Comments: 0

Things are getting far more complicated as we move down to 7nm & 5nm but the tolerances of some of the physical effects that we have been measuring in the past are much tighter than they were at the older nodes. How do we track all that? What we see is that as we descend through the advanced nodes, say from 16nm down to 12nm, 7nm and more recently 5nm, we see that gate density starts to ... » read more

Building Access Control With Free Topology
By Jen Bernier-Santarini - 14 Nov, 2019 - Comments: 0

For facilities managers of large buildings and campuses, security and access control are huge challenges. Authorized persons come and go so privileges must be granted and revoked; different employees, students and visitors may all have different levels of privilege/access; the access cards themselves must be authenticated; and the list goes on. This is in the face of ever-escalating security th... » read more

Building Quantum Espresso With Arm Compiler
By Arm - 14 Nov, 2019 - Comments: 0

This resource topic addresses how to build Quantum Espresso with Arm Compiler for HPC. Quantum Espresso is an integrated suite of open-source computer codes for electronic-structure calculations and materials modeling at the nanoscale. It is based on density-functional theory, plane waves, and pseudopotentials. Click here to read more. » read more

Speeding Up 3D Design
By Brian Bailey - 14 Nov, 2019 - Comments: 0

2.5D and 3D designs have garnered a lot of attention recently, but when should these solutions be considered and what are the dangers associated with them? Each new packaging option trades off one set of constraints and problems for a different set, and in some cases the gains may not be worth it. For other applications, they have no choice. The tooling in place today makes it possible to de... » read more

Power Complexity On The Rise
By Ann Mutschler - 14 Nov, 2019 - Comments: 0

New chip architectures and custom applications are adding significant challenges to chip design and verification, and the problems are becoming much more complex as low power is added into the mix. Power always has been a consideration in design, but in the past it typically involved different power domains that were either on, off, or in some level of sleep mode. As hardware architectures s... » read more

Manufacturing Bits: Nov. 13
By Mark LaPedus - 13 Nov, 2019 - Comments: 0

Power beams The U.S. Naval Research Laboratory and PowerLight Technologies have demonstrated the ability to transmit energy using a long-range, free-space power beaming system. The system is being developed as part of the Power Transmitted Over Laser (PTROL) project. The system consists of two 13-foot-high towers. One tower consists of 2-kilowatt laser transmitter. The other tower consist o... » read more

Performance Analysis Of Electric Motors For EV Powertrains
By Ansys - 13 Nov, 2019 - Comments: 0

Developing a battery EV powertrain is a complex systems problem. This technical paper examines the design and development of electric motors in an EV powertrain, showing how the different design choices — such as motor topology, winding type and cooling system — can be compared and evaluated considering their overall system impact. ANSYS Motor-CAD simulations can help engineers determine wh... » read more

Using Machine Learning To Break Down Silos
By Ed Sperling - 13 Nov, 2019 - Comments: 0

Jeff David, vice president of AI solutions at PDF Solutions, talks with Semiconductor Engineering about where machine learning can be applied into semiconductor manufacturing, how it can be used to break down silos around different process steps, how active learning works with human input to tune algorithms, and why it’s important to be able to choose different different algorithms for differ... » read more

LonWorks + BACnet: Multi Protocol Field Bus Solution
By Adesto Technologies - 13 Nov, 2019 - Comments: 0

A fully interoperable multi-protocol field bus implemented by Adesto's partner Western Allied combines two popular Smart Building protocols in a single network. This whitepaper explains how. » read more

Addressing Pain Points In Chip Design
By Ed Sperling - 13 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx, Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy