The economics are not yet clear for industrial or consumer electronics.
Chiplets are emerging as a significant new phase in the evolution of the semiconductor market, providing a way to continue scaling performance well beyond the size limitations of a reticle. But that improvement comes with a high price tag and a lot more complexity, which so far has limited adoption.
One of the main reasons for the cost increase is the need for advanced packaging when employing chiplets, which represents a fundamental shift in how semiconductors are designed, built, and tested. It requires extra time, effort, expertise, and experimentation, because there are no set recipes. Standards eventually may help mitigate the risk, but it’s not clear whether the cost of advanced packaging will ever beat that of traditional packaging.
“Nobody really knows when chiplets will make sense in automotive, industrial, and similar markets,” said Andy Heinig, head of efficient electronics at Fraunhofer IIS’ Engineering of Adaptive Systems Division. “And it’s not only standards. It’s more or less a discussion about when it really makes economic sense.”
Chiplets are definitely good at some things
Chiplets largely have been motivated by designs where cost is less important than viability and/or performance. “We see a lot of progress on chiplets in the data center, but this is motivated by the fact that a single chip is too large,” said Heinig. “Now you reach the reticle size, and it’s easy to cut this one chip into two pieces.”
In general, the smaller and more specific the die, the higher the yield, which in turn can offset some of the additional costs of advanced packaging. The fact that the early players are still moving forward suggests this is a net win.
There is still a benefit to scaling some circuits. Advanced process nodes can provide performance and power improvements that are not available in older processes. Leading-edge systems requiring such performance have a choice — build a monolithic die or employ chiplets. The advantage of chiplets is that not all circuits need to be built at the same node. If they can be manufactured with less expensive processes and lower mask costs, that helps the overall cost of the silicon implementation. As a result, some silicon development should be less expensive, although the additional effort necessary for an advanced-package design may consume some of those savings.
Chiplets also excel where a given chiplet can be designed to serve in multiple products. The less-expensive initial development now can be amortized over multiple products, further reducing cost.
“Maybe you have an application where the I/Os really aren’t changing, and you’ll re-use those chiplets for maybe two or three generations of products,” said Rob Kruger, product management director at Synopsys. “Then you’re redesigning only the processing chiplet where the algorithm changes. Once you have the set of chiplets and they all work together, then you can mix and match and scale from low to medium to high end.”
What if cost is a primary consideration?
Many of the benefits outlined above reflect cost savings, but only under certain conditions, such as:
Analog and other non-CMOS functionality, such as memory, MEMS, and optical, also can benefit from a chiplet-based approach. For years, the industry has been integrating CMOS, analog, and memory in microcontrollers (MCUs), and they often are used in cost-conscious systems. So there is some history showing monolithic integration at these price points can be cost-effective. In contrast, the integration of MEMS and optical with CMOS beyond sensor/actuator signal conditioning and control has been limited.
Defense markets also provide some opportunity, and agencies such as DARPA have been a force in moving chiplet technology forward with some focus on price sensitivity. But interest in chiplets falls off significantly in price-sensitive markets.
Can packaging costs come down far enough?
Consumer and industrial customers heavily focus on MCUs, which often are priced at less than $10. Cost savings at any level is not a bad thing, and disaggregating a monolithic die might provide some nominal cost savings based on slightly improved yields. But most cost-conscious dies yield well, anyway, so that savings may not amount to much.
The big change when disaggregating a die is the move from standard packaging to advanced packaging. And there’s no question that advanced packaging today is far more expensive than standard packaging. The cost of the package itself may be greater than the average price of some of these chips.
“I made a presentation at the Chiplet Summit, and I mentioned packages with maybe $10 to $20 cost,” said Heinig. “Then a presentation directly after mine mentioned, ‘Sorry, my package can only cost 20 cents.’” That’s a 100X difference.
Interposers add other issues. “The supply of interposers is inaccessible for a lot of people, both in terms of getting in the queue or paying for it if you could get in the queue,” observed David Fromm, COO of Promex.
Efforts are underway by some to move away from silicon interposers to reduce costs. “Now it’s moving to other technology interposers [such as glass], and then to guided substrates with silicon bridges,” said Synopsys’ Kruger.
Whether costs come down enough in the future to change the equation remains to be seen. There is no question that the cost of advanced packaging will decrease after sufficient learning and standard practices are in place. But the real question is whether it will ever drop below the cost of traditional packaging.
“If we’re talking about wire-bonded or even flip-chip packages, probably not,” said Boris Vaisband, EECS assistant professor at UC Irvine. “I doubt we’re going to be designing chiplet-based dishwasher chips or really low-end stuff. I do believe that there’s room for that at mid-scale.”
Bill Chen, fellow and senior technical advisor at ASE, agreed regarding the likelihood of beating the cost of simple wire-bonded packaging. “When I think about wire bonds, I think about our factory in Taiwan, and it is highly automated,” he said. “It’s operated by one operator for 20 or 30 wire bonders. So it’s hard for me to think that automating advanced-package assembly can beat those factories.”
Can integration be the cost savings?
Lower-cost systems that traditionally employ multiple chips on a PCB also could benefit from chiplets. In some cases, that benefit may be a space savings. If that’s the situation, then cost is taking a back seat to area in terms of priority. But in many cases, price still will be a barrier.
The key variable here is whether integration can reduce cost, and that depends on what’s being integrated and the difficulty of doing so. If the total cost of the chips being integrated is low — let’s say in the $10 range — then it will be very difficult to have a cost-effective chiplet-based product in the short term. As advanced-packaging costs come down, any cost increase is likely to shrink, making this less of a burden.
If one of the integrated chips is a more expensive chip, then adding a couple other chiplets to that package might be a winning strategy, possibly lowering overall costs. “That application will have a lower cost because you integrated everything,” observed ASE’s Chen.
Thinking longer term
An MCU being disaggregated into multiple chiplets may well add cost in one generation. But if done strategically, circuits that aren’t likely to change, such as well-established I/Os, can be segregated onto chiplets for reuse in future versions. In those future versions, only the chiplets with changing functions would require redesign, and that development project will require significantly less investment than the first one.
Can the anticipated savings in Gen2 be factored into the price of Gen1 to keep it competitive? If not, and if you’re the first one doing this among your competitors, will the higher Gen1 price keep it from becoming successful and threaten Gen2 as a project? If your Gen1 comes ahead of others, you’ll be alone on higher costs.
Of course, if your competition makes its move on Gen2, then their higher Gen2 costs will hit when your lower Gen2 costs hit — but only if Gen1 was originally successful enough to merit a Gen2.
Fig. 1: Chiplet economics may require multiple generations to yield results. A disaggregation project involves the design of all chiplets. The following generation may allow some Gen1 chiplets to be re-used in Gen2. Source: Bryon Moyer/Semiconductor Engineering
And if your competition waits too many generations to make the move, will the Gen2 and beyond savings allow you to price competitively with monolithic implementations? This is a definite example of timing being important and the risks of being too early.
“You might be punished for making the leap to chiplets before so many competitors, unless you’re offering some kind of functionality that couldn’t be done the other way,” said Kruger.
Can we even calculate savings for automotive?
The automotive market has indicated interest in chiplets, as well. How it would fare here is less clear. Some advanced driver-assistance systems (ADAS) require large chips, so they would benefit in the same way data center chips do.
“Without chiplets you will get to the reticle limit, because if you want to put not only the CPUs, but also the AI NPUs and the memory and the vision and the DSP all together on the same chip, you cannot do it,” said Moshiko Emmer, distinguished engineer, silicon solutions group at Cadence. “It’s too big.”
Automotive is an example of what some are calling “physical AI,” which also includes robots and drones. Chiplets employed in any of these markets will differ from how they’ve evolved in the data center.
“In data centers, you’ll have one CPU chiplet that is duplicated many times to increase the number of cores,” noted Emmer. “In the physical-AI case, you will have a set of different chiplets, each of them serving a different family of functions. But you can put more functions on the same platform.”
Differentiation also matters, and where OEMs can compete has changed. “Until now, the competition between, say, BMW, Mercedes, and Audi has been how strong the engine is,” Emmer said. “Once they are all EVs, the competition needs to be on other stuff such as ADAS or infotainment. So there’s a lot of interest from OEMs in taking different chiplets from different vendors.”
Not all cars are fancy
Heinig pointed to a practical issue if ADAS is the focus. “What we’ve discussed with the car makers is that only 5% of cars really have the full ADAS functionality because it’s so expensive. This ADAS functionality is a niche market, and this is a big problem. You need radar, you need cameras, maybe lidar. Each of the sensors costs $500 or $200, and you need 10 or 15 of those sensors. And now everybody has figured out it’s very, very expensive.”
So what about the more prosaic chips that do the grunt work of getting a vehicle from here to there, whether a cheap beater car or a high-flying limo? This turns out to be harder to answer because cost models are murky. “You have to compare cost models, and each car manufacturer has a different cost model,” said Heinig. “Every OEM is doing the cost calculation differently. Some of the costs are pushed to tier one or to tier two, and it’s really difficult to understand the models. We struggle to have a cost model and to explain the advantages of chiplets.”
Cadence is developing a chiplet-based automotive reference design, and it is taking some of this cost sensitivity into account, making available a smaller version for traditional packaging. “The main chiplet contains most of the functions, along with an application cluster,” explained Emmer. “So it can behave as a standalone system, and you can package it standalone.”
The automotive market has notoriously long lead times, based partly on the safety-related nature of the business. But strategic changes come slowly, as well, and deciding to move to chiplets is a big change. “It takes time for automotive companies to decide that this is the way to go, and I don’t see that as yet,” said Chen.
Which applications would a chiplet marketplace serve?
Today’s chiplet designs are overwhelmingly dominated by large semiconductor and systems companies that can afford to fund the multiple development projects for the chiplets, as well as the packaging. These companies largely control every significant component inside the package.
“The big dataset guys are going to design what they need, and they can foot the bill and get the absolute performance they need,” noted Kruger. “They may not even need open compatibility, as long as it’s compatible in their system.”
This scenario differs dramatically from that envisioned by those looking forward to an open chiplet marketplace, where hardened silicon functions can be obtained in the same way that soft IP functions are purchased today.
That vision serves companies with good ideas but smaller budgets. Instead of having to develop every die for the package, the company can focus on differentiating silicon that implements its good ideas, reaching out to the marketplace for the other standard stuff it needs. This can be particularly compelling for startups.
“The [small] guys would like to have this open chiplet ecosystem so they don’t have to do everything themselves,” said Kruger. “And they probably can’t foot the bill for the latest-generation process technology, tape-outs, and multiple chiplets. So they would like to have this ecosystem.”
But if answers to the prior questions say that cost-conscious designs won’t benefit from chiplets, does that then eliminate the very users of that marketplace? Will investors support a more expensive approach if the motivation isn’t existential? Would a chiplet version ever qualify as being minimally viable?
Cost isn’t the only limiter
Today two factors limit engagement with chiplets. One is cost. The other is risk, which is an issue because today each company is inventing its own flow, and each new project may stimulate the need for yet other new flows. “It’s not just the cost,” Promex’s Fromm pointed out. “It’s the risk of what happens if your product development crashes and burns. That’s a bad place to be. Assembling these devices is going to be more expensive than a standard device, obviously, but it’s more than that. You have to think about how you’re going to test it. How do you manage power? How do you manage heat? How do you manage the physical impact of assembly warpage and mismatches and reliability? Maybe the cost is reasonable, or it’s close to par, but the risk just isn’t worth it.”
Few companies have the spare resources to risk that. And by modern metrics, spare resources indicate inefficiency. No one is held to a higher standard in that regard than startups, where the mandate is to focus on a minimum viable product in as little time as possible.
It’s this risk that the technical discussions and standards will address. Once there are fewer unknowns in the process, more companies will be willing to engage.
Asking the quiet part out loud
There are many barriers to a chiplet marketplace today, and much discussion and effort goes toward addressing them. “We’re still trying to define this correct level of abstraction that is called chiplets,” noted UC Irvine’s Vaisband.
But those are largely related to technical issues. What standards will ensure interoperability when interconnecting chiplets? What design flows are necessary to make first-pass success more likely? What reliability challenges must be solved?
There’s one question that one rarely hears asked out loud. If we solve all these technical hurdles, can the result ever be cost-competitive with the status quo, even in cost-conscious markets? If we invest significant sums in setting up the necessary infrastructure, will the economics favor chiplet design? If you build it, will they come?
Kruger asked the question another way with respect to the marketplace, “Will people give up cost for this easier development environment? In some cases yes, in some cases no.”
Some believe the economic payoff will materialize, even if they can’t point to a reason now. “Judging by the history of technology, there will be a breakthrough,” said Fromm.
There’s a chance, however, that chiplets will remain a viable choice only in certain markets. “It’s good that we are focusing chiplets on specific markets, because if you try to push chiplets everywhere, it’s going to be very hard,” said Emmer. “I still see a market for basic microcontrollers if they’re very cheap. If there is no problem, we don’t need to fix it.”
Related Reading
Chiplets Add New Power Issues
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What Exactly Are Chiplets And Heterogeneous Integration?
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Challenges In Managing Chiplet Resources
The chip industry is exploring multiple avenues for simplifying multi-die integration, but difficulties remain for optimizing designs.
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