category: Power Source

category: IoT, Security & Automotive

Reliability Challenges In 16nm FinFET Design
By Arvind Vel - 10 Oct, 2013 - Comments: 1

As the IC industry rapidly adopts the 16nm technology node, IC designers are faced with a new wave of reliability challenges. The 16nm node has introduced several changes in the way that the devices are fabricated and how the metal stack-up is built. On one hand designers gain speed, leakage and density improvements. On the other, reliability engineers need to address the narrowing electromigra... » read more

Need For Unified Chip-Package Analysis
By Chris Ortiz - 12 Sep, 2013 - Comments: 0

For anyone involved in the system-on-chip (SoC) design cycle over the past few years, it is easy to see that the functionality of the chip has become more diverse with the addition of new features and duplication of main functions to drive higher throughput. This trend coupled with the need to maintain low power through various techniques such as voltage islands and power and clock gating have ... » read more

Next-Gen Distributed Machine Processing
By Rama Nemalikanti - 08 Aug, 2013 - Comments: 0

By Rama Nemalikanti The gate count increase of chip designs, especially for mobile application processor system-on-chips (SoCs), is being closely tracked to help guide the development of supporting design and simulation tools. However, sign-off quality power integrity analysis requires the inclusion of the entire integrated circuit (IC) design, along with its associated package and printed cir... » read more

RTL Design-for-Power In Mobile SoCs
By Preeti Gupta - 11 Jul, 2013 - Comments: 0

If you are one of the more than 2 billion smartphone users today, it is hard to imagine life without one! Breaking new frontiers, wearable smart devices and the Internet of things are the latest buzz. Mobile system-on-chips (SoCs) continue to clock faster and pack more functionality, yet are required to consume lower power for battery life and thermal considerations. Power consumption is a k... » read more

Challenges In IC And Electronic Systems Verification
By Aveek Sarkar - 13 Jun, 2013 - Comments: 0

In the first two parts of this series, we reviewed the challenges design teams face as they grapple with increasing power consumption, tighter schedules and the drive to reduce costs. Both a top-down and a bottom-up analysis framework were proposed to help control these challenges. In part 2 of this series, specific challenges were outlined including power budgeting, power and signal integrity,... » read more

Challenges In IC And Electronic Systems Verification
By Aveek Sarkar - 09 May, 2013 - Comments: 0

Power efficiency, unrealistic schedules, and cost-down considerations are increasingly the top challenges design teams must meet to deliver next generation electronic systems, whether it is for the mobile, server, or automotive market. In addition, a successful chip tapeout does not guarantee the eventual end-product’s success—there are many variables to take into account. In the first p... » read more

Challenges In IC And Electronic Systems Verification
By Aveek Sarkar - 11 Apr, 2013 - Comments: 0

By Aveek Sarkar Designing successful electronic systems that can meet the needs of a challenging and quickly evolving mobile market requires design teams to solve critical problems such as power efficiency, unrealistic schedules, and cost-down considerations. In this first of a three-part series, we will look at these challenges. Part 1: The Growing Challenges Designing electronic systems ... » read more

Shock Value
By Norman Chang - 14 Mar, 2013 - Comments: 0

By Norman Chang Chip-Package-System (CPS) ESD simulation enables system-wide ESD robustness validation, a common challenge in automotive and aerospace applications. To enable CPS ESD analysis requires an accurate chip electrostatic discharge (ESD) model and a comprehensive system-level ESD methodology. Using an accurate ESD chip model provides the following three benefits. First it helps de... » read more

Clean Your Clock
By William Ruby - 14 Feb, 2013 - Comments: 0

Lowering power consumption seems to be on every designer’s mind these days. And yet when asked about applying low-power design techniques, many engineers respond, “Well, we do clock gating ... and that’s about it.” Clock gating is low-hanging fruit when it comes to low-power design. Clock gating is also well automated, as witnessed by capabilities in modern logic synthesis tools. The... » read more

Reducing Cost And Mitigating Risk
By Aveek Sarkar - 17 Jan, 2013 - Comments: 0

By Aveek Sarkar & Lawrence Williams How will you design your next generation of products and keep pace with rapidly evolving market needs, while managing your margins? Many industries face these same design challenges. The speed of new product development—especially for meeting complex new design requirements—has never been more demanding. Historically, the rise in product development ... » read more

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