Inside Chip R&D


Semiconductor Engineering sat down to discuss R&D challenges, EUV and other topics with Luc Van den hove, president and chief executive of Imec, an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Clearly, Moore’s Law is slowing down. The traditional process cadence is extending from 2 years to roughly 2.5 to 3 years. Yet, R&D is not slowing down, right? ... » read more

CMOS Image Sensors (CIS): Past, Present & Future


Over the last decade, CMOS Image Sensor (CIS) technology has made impressive progress. Image sensor performance has dramatically improved over the years, and CIS technology has enjoyed great commercial success since the introduction of mobile phones using onboard cameras. Many people, including scientists and marketing specialists, predicted 15 years earlier that CMOS image sensors were going t... » read more

Going Vertical?


The topic of transistor scaling has been traditionally covered at SEMICON West in its own right. This year’s event, however, will also explore scaling in 3D, as well as using packaging to accomplish similar objectives. Along with traditional transistor scaling, speakers will tackle design and metrology considerations for scaling the package, and address the economic decisions that inform dens... » read more

Fab Spending Hits New High


The latest update to the World Fab Forecast report, published on May 31, 2017 by SEMI, reveals record spending for fab construction and fab equipment. Korea, Taiwan, and China all see large investments, and spending in Europe has also increased significantly. In 2017, over US$49 billion will be spent on equipment alone, a historic record for the semiconductor industry. Spending on new fab cons... » read more

Making Interconnects Faster


In integrated circuits, interconnect resistance is a combination of wire and via resistance. Wire resistance of a conductor depends on several factors, one of which is the electron scattering at various surfaces and grain boundaries. Via resistance, on the other hand, is a function of the thickness or resistivity of the layers at the bottom of the via through which current must travel. T... » read more

Will Higher Production Costs Hamper IoT Growth?


No question, 2017 is expected to be a good year for the semiconductor industry. Semiconductor revenues for 2017 are expected to increase more than 9% this year. A 6% increase in unit sales, as well as higher average selling prices for memory products, will help drive the revenue growth rate to its highest level since 2010. Wafer demand is forecast to grow by almost 8%. The higher revenue growth... » read more

High-Stakes Litho Game


The commercial introduction of EUV looks all but assured these days. There is enough history to show it works. Uptime and throughput are improving, and systems are shipping today. The question now is how to measure its success. In the short-term, this is a fairly simple financial exercise for companies like ASML and Zeiss, which have been closely collaborating to get these massive systems ou... » read more

Notes From The Chip Beat


Over the last several months, I’ve attended a number of conferences, such as IEDM, SPIE, the FD-SOI Summit and others. At each conference, there is a dizzying amount of information and data. Eventually, some information turns into an article, while most ends up buried in a reporter’s notebook. In any case, here are five observations I’ve made, based on those and other events in the pa... » read more

The Future Of Patterning


Greg McIntyre, director of advanced patterning at imec, offers his thoughts on what it’s like to work at one of the world’s leading nanoelectronics R&D centers, as well as the importance of eBeam technology to lithography and mask making, what’s driving up confidence in EUV, and the latest on imec’s joint venture with JSR in EUV resist development. [youtube vid=q8cA_9rWecU] » read more

What Drives SADP BEOL Variability?


Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies. For the 7nm technology node, patterning requirements include a metal pitch of 40nm or less. This ... » read more

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