category: Test, Measurement and Analytics

category: IoT, Security & Automotive

The Next Generation of Testbench Debug Productivity
By Synopsys - 08 Jun, 2021 - Comments: 0

It is widely accepted that verification consumes at least sixty percent of time and resources on most semiconductor development projects. This statistic has been borne out by many industry surveys over the last twenty years. Verification technology has had to evolve to accommodate ever larger and more complex designs. Innovations such as constrained-random simulation and the Universal Verificat... » read more

Monitoring Performance From Inside A Chip
By Ed Sperling - 01 Jun, 2021 - Comments: 0

Deep data, which is generated inside the chip rather than externally, is becoming more critical at each new process node and in advanced packages. Uzi Baruch, chief strategy officer at proteanTecs, talks with Semiconductor Engineering about using that data to identify potential problems before they result in failures in the field, and why it's essential to monitor these devices throughout their... » read more

Managing Wafer Retest
By Anne Meixner - 19 May, 2021 - Comments: 1

Every wafer test touch-down requires a balance between a good electrical contact and preventing damage to the wafer and probe card. Done wrong, it can ruin a wafer and the customized probe card and result in poor yield, as well as failures in the field. Achieving this balance requires good wafer probing process procedures as well as monitoring of the resulting process parameters, much of it ... » read more

Recalculating The Cost Of Test
By Ed Sperling - 11 May, 2021 - Comments: 0

The cost of test is rising. For decades, test was limited to a flat 2% of the cost of designing and manufacturing a chip. Today, no one is quite sure what that cost really is, and there doesn't seem to be any single formula for determining it. In some cases, there isn't even a sense of urgency to finding out. Several significant changes are occurring that make any formula difficult to cal... » read more

Understanding Optical Inspection For CIS
By Woo Young Han - 11 May, 2021 - Comments: 0

The demand for smartphone cameras, video conferencing, surveillance and autonomous driving has fueled explosive growth of CMOS image sensor (CIS) manufacturing in the last decade. While CIS becomes an increasingly important element in the production of today’s consumer electronics, there are unique challenges in production that must be addressed. As pixel sizes shrink, we see an inverse relat... » read more

In-Chip Sensing And PVT Monitoring: Not Just An Insurance Policy
By Ramsay Allen - 11 May, 2021 - Comments: 0

You wouldn’t drive an expensive car without insurance or take a flight in an aircraft without performing instrument and control surface checks. So why would you take the risk of designing a multi-million dollar advanced node semiconductor device without making sure you are aware of, and able to manage, the dynamic conditions that had the potential to make or break a silicon product? Advanced... » read more

Chip Monitoring And Test Collaborate
By Bryon Moyer - 11 May, 2021 - Comments: 0

As on-chip monitoring becomes more prevalent in complex advanced-node ICs, it’s easy to question whether or not it conflicts with conventional silicon testing. It might even supplant such testing in the future. Or alternatively, they could interact, with each supporting the other. “On-chip monitors provide fine-grained observability into effects and issues that are otherwise difficult or... » read more

Testing AiP Modules In High-Volume Production
By Jose Moreira - 11 May, 2021 - Comments: 0

Far-field and radiating near-field are two options for high-volume over-the-air (OTA) testing of antenna-in-package (AiP) modules with automated test equipment (ATE) [1]. In this article, we define an AiP device under test (DUT) and examine the measurement results from both methods. Creating an AiP evaluation vehicle Proper evaluation of an ATE OTA measurement setup requires an AiP module. Us... » read more

Testing Analog Circuits Becoming More Difficult
By Susan Rambo - 11 May, 2021 - Comments: 1

Foundries and packaging houses are wrestling how to control heat in the testing phase, particularly as devices continue to shrink and as thermally sensitive analog circuits are added into SoCs and advanced packages to support everything from RF to AI. The overriding problem is that heat can damage chips or devices under test. That's certainly true for digital chips developed at advanced node... » read more

Chasing Test Escapes In IC Manufacturing
By Anne Meixner - 11 May, 2021 - Comments: 0

The number of bad chips that slip through testing and end up in the field can be significantly reduced before those devices ever leave the fab, but the cost of developing the necessary tests and analyzing the data has sharply limited adoption. Determining an acceptable test escape metric for an IC is essential to improving the yield-to-quality ratio in chip manufacturing, but what exactly is... » read more

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