category: System-Level Design

category: IoT, Security & Automotive

Functional Safety Implementation Goes Mainstream
By Mary Ann White - 24 Oct, 2019 - Comments: 0

Electronics engineers are being thrust into the automotive market like never before. The move to electrify automobiles, along with the advent of self-driving cars, means that silicon designers will be designing ever more sophisticated automotive ICs. But cars aren’t like most other electronic systems; it’s imperative that they cause no harm should they fail. This brings us to the realm o... » read more

HW/SW Co-Verification For Hybrid Systems
By Wojtek Lewandowski - 24 Oct, 2019 - Comments: 0

Heterogeneous SoC architectures such as Zynq have become very popular recently due to the combination of programmable logic (FPGA) and processing system (ARM) integrated into a single chip. Developing a design using such hybrid systems causes complexity in design verification stages. To help address this complexity, Aldec introduced support for QEMU for co-verification in our HES.Proto-AXI host... » read more

IP Management And Development At 5/3nm
By Ann Mutschler - 24 Oct, 2019 - Comments: 1

The growing complexity of moving to new process nodes is making it much more difficult to create, manage and re-use IP. There are more rules, more data to manage, and more potential interactions as density increases, both in planar implementations and in advanced packaging. And the problems only get worse as designs move to 5nm and 3nm, and as more heterogeneous components such as accelerato... » read more

RISC-V Challenges And Opportunities
By Ed Sperling - 24 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss open instruction set hardware and the future of RISC-V with Ben Levine, senior director of product management in Rambus' Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation. (L-... » read more

Using HLS To Improve Algorithms
By Zubair Wadood - 24 Oct, 2019 - Comments: 0

Can an HLS optimization tool outperform expert-level hand-optimizations? A recently published white paper examines how SLX FPGA is used to optimize a secure hash algorithm. T the results are compared to a competition-winning hand-optimized HLS implementation of the same algorithm. This approach provides a nearly 400x speed-up over the unoptimized implementation and even outperforms the hand ... » read more

5G Verification Is Impossible Without Emulation
By Mentor, a Siemens Business - 23 Oct, 2019 - Comments: 0

Emulation, combined with a rich assortment of virtualized versions of the many protocols that 5G will require, is the only practical way of ensuring that the first round of silicon built will be the production version, able to handle all of the functions and configurations that it might be faced with and having the tight performance characteristics needed for successful integration into a 5G sy... » read more

Compressing Datasets Created During Silicon Design
By Cadence - 23 Oct, 2019 - Comments: 0

Authors: Guru Rao, Distinguished Engineer; Shakir Abbas, Software Engineering Group Director; Mohammad Mirfendereski, Configuration Management Architect; Cadence. Harsh Sharangpani, CEO and CTO; Rajesh Patil, VP-Business Development; Ascava. During the design cycle for modern semiconductor components, a very large amount of data is generated and stored, often accumulating to hundreds of tera... » read more

Using SLX FPGA For Performance Optimization Of SHA-3 For HLS
By Silexica - 23 Oct, 2019 - Comments: 0

Author: Zubair Wadood SLX FPGA facilitates converting your C/C++ project into an FPGA bitstream easier and with higher performance. Leveraging standard HLS (High Level Synthesis) tools from FPGA vendors, SLX FPGA tackles the challenges associated with the HLS design flow. In this paper, the results of an SLX FPGA-optimized implementation of a Secure Hash Algorithm (SHA-3; also known as Kecca... » read more

Blog Review: Oct. 23
By Jesse Allen - 23 Oct, 2019 - Comments: 0

ANSYS' Magdy Abadir digs into the challenges associated with identifying and modeling electromagnetic crosstalk and the architectural and design trends that contribute to it. Cadence's Paul McLellan listens in as automotive security expert Charlie Miller points to how close we are to Level 4 autonomy and where in a car attack surfaces lie. Mentor's Brent Klingforth checks out the process ... » read more

Accelerating Toshiba’s Advanced System-on-Chip (SoC) Design with Synopsys’ Fusion Compiler
By Synopsys - 23 Oct, 2019 - Comments: 0

Authors: Mitchy M. Mitsuyasu, Senior Specialist, Semiconductor R&D, Toshiba Electronic Device & Storage Corp.; Akira Nikaido, Director Product Marketing, Synopsys. Toshiba Electronic Devices & Storage Corporation, part of the broader Toshiba, Kawasaki Japan, has long been a technology leader in Advanced SoCs spanning multiple, key market verticals. This includes automotive, communications, I... » read more

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