category: System-Level Design

category: IoT, Security & Automotive

AI, Rising Chip Complexity Complicate Prototyping
By Karen Heyman - 24 Aug, 2023 - Comments: 0

Prototyping, an essential technology for designing complex chips in tight market windows, is becoming significantly more challenging for the growing number of designs that include AI/ML. Prototyping remains one of the foundational pillars of the whole shift left movement, allowing software to be developed and tested before actual silicon is available. That, in turn, enables multiple teams t... » read more

Why Shift Left?
By Michael White - 24 Aug, 2023 - Comments: 0

As every integrated circuit (IC) design company knows, the faster a design can progress from implementation to signoff verification, the better the chances are of meeting tapeout schedules. Meeting tapeout schedules improves a company’s chances of reaching their market targets. But as companies create larger and more complex ICs and move to advanced process nodes, the challenge of achieving t... » read more

Preparing For Commercial Chiplets
By Ed Sperling - 24 Aug, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the path to commercialization of chiplets with Saif Alam, vice president of engineering at Movellus; Tony Mastroianni, advanced packaging solutions director at Siemens Digital Industries Software; Mark Kuemerle, vice president of technology at Marvell; and Craig Bishop, CTO at Deca Technologies. What follows are excerpts of tha... » read more

The Power Of Computational Software: From Revolutionizing Chips To Cancer Research
By Reela Samuel - 24 Aug, 2023 - Comments: 0

This post is an excerpt from the keynote presentation at CadenceLIVE India, given by Nimish Modi, senior vice president and general manager of Strategy and New Ventures at Cadence. The semiconductor industry has grown significantly lately but follows a cyclical pattern marked by fluctuations. Currently, we are witnessing a macro-level correction aimed at resolving inventory imbalances. N... » read more

Speeding Up Design Closure
By Ed Sperling - 23 Aug, 2023 - Comments: 0

Increasing complexity and smaller process nodes make it far more difficult to achieve design closure for chips. There are more physical effects to model, including noise, cross-talk, and double switching effects, all of which can slow the design process. Solaiman Rahim, vice president of engineering for Synopsys’ EDA Group, talks about why it’s so important to analyze violations in design, ... » read more

Accelerating Monte Carlo Simulations For Faster Statistical Variation Analysis, Debugging, And Signoff Of Circuit Functionality
By Cadence - 23 Aug, 2023 - Comments: 0

Over the years, semiconductor process nodes have been scaled aggressively, with device dimensions now approaching below 5nm. This, along with lower device operating voltages and currents, has allowed modern integrated circuits (ICs) and system-on-chip (SoC) designs to integrate more devices in a smaller chip area without compromising on lower power consumption and optimal performance. However, ... » read more

Stop-For-Top IP Model To Replace One-Stop-Shop By 2025… And Support The Creation Of Successful Chiplet Business
By Alphawave Semi - 23 Aug, 2023 - Comments: 0

The One-Stop-Shop model has allowed IP vendors of the 2000’s to create a successful IP business, mostly driven by consumer application, smartphone or Set-Top-Box. The industry has dramatically changed, and in 2020 is now driven by data-centric application (datacenter, AI, networking, HPC…), requiring best-in-class, high-performance IP developed on bleeding edge technology nodes. That’s wh... » read more

Power Supply Noise Effects On Jitter In Clock Synchronous Systems With Emphasis On Memory Interfaces
By Synopsys - 23 Aug, 2023 - Comments: 0

In today's fast-paced digital world, the performance and capacity of high-speed memory has become crucial for a wide range of applications, from personal computing devices to data centers and high-performance computing systems. Designers face challenges in optimizing their designs for speed, power efficiency, and reliability — all while ensuring robustness in the face of power supply noise. T... » read more

A Design Flow For Critical Embedded Systems
By Arteris - 23 Aug, 2023 - Comments: 0

Learn how IP encapsulation/packaging and interoperability using IP-XACT enabled automation in a complex verification & validation flow for aeronautical systems. Includes usage of these capabilities integrated using Arteris SoC integration technology: HW/SW codesign RTL, SystemC TLM and PSL Instruction Set Simulators Click here to read more. » read more

An Ideal Architecture For Always-On Camera Subsystems
By Expedera - 23 Aug, 2023 - Comments: 0

Always-sensing camera implementations offer a wealth of user experience advantages but face significant power, latency, and privacy concerns if not done right. To be successful, always-sensing camera subsystems must be architected to preserve battery life and to ensure privacy and security while delivering key user experience improvements. In a joint white paper with Rambus, Expedera discuss... » read more

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