IEDM: TSMC N3 Details


I attended IEDM in San Francisco in December. There were two presentations about TSMC's N3 process. This is actually a bit of a misnomer since TSMC has two N3 processes, one simply called N3. The other (the second generation) is called N3E. The two papers were: Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond A 3nm CMOS FinFl... » read more

Benefits Of A Silicon-Proven 800G Ethernet Solution For High-Performance Computing


The evolution of high-speed Ethernet began in 2014 when Arista, Broadcom, Microsoft, Mellanox and Google formed the Ethernet Consortium, now called the “Ethernet Technology Consortium.” Since then, the technology has been adopted by more than 45 members. The push for 200G, then 400G, and now 800G Ethernet is driven by the insatiable need to process and transmit high-performance workloads in... » read more

Power Issues Causing More Respins At 7nm And Below


Power consumption has been a major design consideration for some time, but it is far from being a solved issue. In fact, an increasing number of designs have a plethora of power-related problems, and those problems are getting worse in new chip designs. Many designs today are power-limited — or perhaps more accurately stated, thermal-limited. A chip only can consume as much power as it is ... » read more

5 Takeaways From The RISC-V Summit


After an intense week at the 2022 RISC-V Summit in San Jose, California, I am fueled with energy and positive thoughts. I had plenty of time to reflect on the event, which was unique in many ways. A lot happened in a few days for us at Codasip as well as for the wider RISC-V community, and here are 5 things I will remember from this conference. 1. RISC-V is inevitable If you have read our a... » read more

CXL Picks Up Steam In Data Centers


CXL is gaining traction inside large data centers as a way of boosting utilization of different compute elements, such as memories and accelerators, while minimizing the need for additional racks of servers. But the standard is being extended and modified so quickly that it is difficult to keep up with all the changes, each of which needs to be verified and validated across a growing swath of h... » read more

The QA Exchange Deck In Solido Crosscheck Enables An IP Qualification Handshake


This paper describes how the QA exchange deck in Siemens EDA’s Solido Crosscheck software can be used to capture and exchange IP qualification requirements. It shows how the QA exchange deck can be used as part of the IP validation framework in Solido Crosscheck to provide an IP signoff handshake between IP suppliers and integrators. To read more, click here. » read more

What Does 2023 Have In Store For Chip Design?


Predictions seem to be easier to make during times of stability, but they are no more correct than at any other period. During more turbulent times, fewer people are courageous enough to allow their opinions to be heard. And yet it is often those views that are more well thought through, and even if they turn out not to be true, they often contain some very enlightening ideas. 2022 saw some ... » read more

The New Convergence: IoT, AI, And 5G Bring Actionable Intelligence To The Factory Floor


Last year, I reflected on the Renesas Renaissance in terms of how our long-term growth strategy is positioning the company as a full-spectrum, global technology solutions provider with an extended physical footprint in the U.S., Europe, and China. Thanks to the acquisitions of Intersil, IDT, Dialog Semiconductor, and Celeno we now have expansive design capabilities that surround our embedded... » read more

Fixed-Point And Floating-Point FMCW Radar Signal Processing With Tensilica DSPs


Automotive Advanced Driver Assistance Systems (ADAS) applications are increasingly demanding radar modules with better capability and performance. These applications require sophisticated radar processing algorithms and powerful Digital Signal Processors (DSPs) to run them. Because these embedded systems have limited power and cost budgets, the DSP’s Instruction Set Architecture (ISA) needs t... » read more

EMC Pre-Compliance Fundamentals


Once you’ve designed your electronic product, it’s time to release it to market, right? Well, not exactly. As with any product development, you need to first test the device you’re designing to validate that it behaves as expected. One such important test that all electronic devices must eventually pass are EMI (electromagnetic interference) compliance tests. Passing EMI tests d... » read more

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