category: System-Level Design

category: IoT, Security & Automotive

RF To mmWave Design For Systems
By Cadence - 23 Feb, 2022 - Comments: 0

RF-enabled next-generation communication systems and connected devices are differentiated by their performance, size, and cost. Traditionally, custom proprietary IC designs, leveraging the latest advanced-node technology, were developed to meet these product requirements. Increasingly these challenges are being met by moving beyond single IC solutions. Today’s electronic systems often integra... » read more

Image Processing For Vision AI
By Renesas - 23 Feb, 2022 - Comments: 0

Recent years have seen an increasing need for Vision AI applications using AI to enable real-time image recognition. Vision AI, which substitutes AI for human visual recognition, requires optimal image processing. Renesas has released RZ/V2M as mid-class, and RZ/V2L as an entry class, Vision AI microprocessors (MPUs). Both products are equipped with DRP-AI which is Dynamically Reconfigurable Pr... » read more

Blog Review: Feb. 23
By Jesse Allen - 23 Feb, 2022 - Comments: 0

Synopsys' Varun Agrawal looks at four new technologies have emerged to support the demands on 5G networks and applications, the challenges in validating all of those technologies together, and what's needed to perform end-to-end testing effectively for 5G O-RAN SoCs. Siemens EDA's Ray Salemi points to how FPGA retargeting could help address supply chain difficulties and some of the challenge... » read more

Week In Review: Design, Low Power
By Jesse Allen - 18 Feb, 2022 - Comments: 0

AMD completed its acquisition of Xilinx. The all-stock deal ended up being valued at approximately $50 billion due to a rise in AMD's share price (the deal was valued at $35 billion when announced). The Xilinx business will become the newly formed Adaptive and Embedded Computing Group (AECG), led by former Xilinx CEO Victor Peng, and will continue its FPGA, adaptive SoC, and software roadmaps a... » read more

Preparing For 3D-ICs
By Ed Sperling - 16 Feb, 2022 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

Blog Review: Feb. 16
By Jesse Allen - 16 Feb, 2022 - Comments: 0

Arm's Mark Nicholson explains the software side of the Morello project to implement a prototype security-focused architecture, presenting a high-level view of the software stacks and discussing the status and roadmap of a range of activities. Synopsys' Ron Lowman finds that as IoT technology and capabilities of portable devices expand, the deployment of 5G networks and interest in AI and aut... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Feb, 2022 - Comments: 0

Nvidia's proposed acquisition of Arm is officially off. The deal faced significant pushback from regulatory agencies in the UK, USA, and Europe, which feared it would reduce or limit competition in areas like data center. Nvidia indicated it would continue working with Arm, and it will retain a 20-year Arm license. (SoftBank will retain the $1.25 billion prepaid by Nvidia.) SoftBank said it wil... » read more

Design Challenges Increasing For Mixed-Die Packages
By Ann Mutschler - 09 Feb, 2022 - Comments: 0

The entire semiconductor ecosystem is starting to tackle a long list of technology and business changes that will be needed to continue scaling beyond Moore's Law, making heterogeneous combinations of die easier, cheaper, and more predictable. There are a number of benefits to mixing die and putting them together in a modular way. From a design standpoint, this approach provides access to th... » read more

Blog Review: Feb. 9
By Jesse Allen - 09 Feb, 2022 - Comments: 0

Arm's Mark Inskip walks through how the Morello program built a demonstration of the architecture that enables fine-grained memory protection and highly scalable software compartmentalization based on the CHERI (Capability Hardware Enhanced RISC Instructions) architectural model, from IP development and SoC design to creating software and a demonstration board. Synopsys' Plamen Asenov and su... » read more

Week In Review: Design, Low Power
By Jesse Allen - 04 Feb, 2022 - Comments: 0

Tools & IP Ansys updated its product suite, adding new tools and workflows in Ansys 2022 R1. It adds Phi Plus meshing technology to improve simulation of PCB and complex 3D IC packaging. It also introduces RedHawk-SC SigmaDVD, a statistically realistic modeling technique to identify the worst-case dynamic voltage-drop in hours and make it possible to achieve near 100% coverage of all relev... » read more

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