category: Top Stories

category: IoT, Security & Automotive

3D Integration: Extending Moore’s Law Into The Next Decade
By Cheryl Ajluni - 27 Aug, 2009 - Comments: 0

By Cheryl Ajluni At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs). The concept of 3... » read more

Restrictive Design Rules, Take Two
By Ed Sperling - 27 Aug, 2009 - Comments: 0

By Ed Sperling For the past couple of years, restrictive design rules have been looming over advanced process nodes as the best way to get a chip out the door with minimal re-spins, on schedule and for the least amount of money. Even with immersion technology, 193nm wavelengths mean the laser beam is entirely too large to create the masks used to create complex systems on chip at 32nm and bel... » read more

Following The WLAN Alphabet To Lower Power
By Ed Sperling - 20 Aug, 2009 - Comments: 0

By Cheryl Ajluni The quest for low power in electronic devices is one that shows no sign of abating any time soon. Pressure for it comes from many different sources, such as the continual drive to pack more functionality into ever smaller, mobile electronic devices. To try and maintain a decent battery life for today’s power-hungry “road-warriors,” engineers have to reduce power con... » read more

An Inside Look At Transaction-Level Power Modeling
By Ed Sperling - 20 Aug, 2009 - Comments: 0

By Ann Steffora Mutschler With design complexity always on the rise and an increasing amount of embedded software encapsulation in designs today, engineering teams need to be concerned with power consumption in the initial architectural design. The only way to do that is to model power consumption at the transaction level. While power is typically estimated after RTL synthesis, the better a... » read more

Mythbusters: Moore’s Law, Low Power And The Future Of Chip Design
By Ed Sperling - 20 Aug, 2009 - Comments: 0

By Ed Sperling Contrary to popular belief, Moore’s Law is not in serious trouble. Nor will active power in most devices be reduced to the millivolt or microvolt level anytime in the near future. And chip design will not disappear, be relegated to the push of a button or move offshore from one low-cost wage location to the next until ultimately it gets to a place where no one is paid a salary... » read more

When It Comes To Intellectual Property, Size Matters
By Various Writers - 19 Aug, 2009 - Comments: 0

By Geoffrey James Intellectual property was once seen as the new growth market for EDA. Dozens of firms – large and small – jumped on the IP bandwagon, attracted to the “build once, sell many times” business model. “As late as 2004, the industry was still thinking that as much as 90% of SoCs would be reused IP,” said EDA consultant Gary Smith. The IP segment, however, hasn�... » read more

Dropping The Voltage: Now What?
By Ed Sperling - 16 Aug, 2009 - Comments: 0

By Ed Sperling Ratcheting down the voltage in an SoC design seems like the simplest way to reduce power consumption, but it doesn’t always work out that way. In fact, reducing voltage can have some rather strange and unexpected effects at all levels of chip design, including testing and debugging. The problem is that not all parts of the chip work the same way without a minimum am... » read more

Who’s In Control Now?
By Ed Sperling - 31 Jul, 2009 - Comments: 0

By Ed Sperling Power is shifting across the design industry in multiple ways and sometimes across multiple continents, driven by complexity and cost pressures and entirely new forms of competition. On one side of the equation, foundries are dictating more of what goes on up front in the design cycle. Design for manufacturing is a prerequisite at 45nm and below, and they’re the ones dictatin... » read more

To Bus Or Not To Bus, That Is The Question
By Ann Mutschler - 31 Jul, 2009 - Comments: 0

By Ann Steffora Mutschler When you hear the words, “block interface,” your ears may not perk up, but as system architects well understand, making the right choice between a bus or non-bus interface on an SoC is absolutely critical to design’s success in terms of power efficiency, reusability and performance. How many of the problems in new chip designs have to do with the interconne... » read more

ESL: Reality, Or A Pigment Of Your Fig Neuton?
By Various Writers - 31 Jul, 2009 - Comments: 0

By Clive "Max" Maxfield One of the questions I am often asked is: "Who's really using ESL tools such as modeling and are there any hiccups in the flow?" Another common question is: "What actually is ESL?" Perhaps we should address the latter question first. To some folks, ESL (electronic system level) means designing at a very high level of abstraction prior to making any hardware-softwar... » read more

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