FinFETs Give Way To Gate-All-Around


When they were first commercialized at the 22 nm node, finFETs represented a revolutionary change to the way we build transistors, the tiny switches in the “brains” of a chip. As compared to prior planar transistors, the fin, contacted on three sides by the gate, provides much better control of the channel formed within the fin. But, finFETs are already reaching the end of their utility as... » read more

Challenges And Approaches To Developing Automotive Grade 1/0 FCBGA Package Capability


Automotive Grade 1 and 0 package requirements, defined by Automotive Electronics Council (AEC) Document AEC-100, require more severe temperature cycling and high temperature storage conditions to meet harsh automotive field requirements, such as a maximum 150°C device operating temperature, 15-year reliability and zero-defect quality level. Moreover, increased integration of device functionali... » read more

Yield Enhancement Technology: Efforts To Suppress Nanosized Particles In Semiconductor Production Equipment


The currently dominant semiconductor process size is in the range between a few and a few dozen nanometers. That means if a nanosized particle smaller than a virus (hereinafter simply “particle”) is present on a silicon substrate, it could cause a defect in the semiconductor device, lowering the production yield (i.e., the percentage of good chips produced in a manufacturing process). Preve... » read more

Survey: eBeam Initiative Luminaries (formerly Perceptions) Survey Results


Survey of 77 industry luminaries across 42 different companies in July 2020 says net neutral COVID-19 business impact by 2021, with 24% positive vs 20% negative predictions. Click here to view the survey results. » read more

Improving EUV Underlayer Coating Defectivity Using Point-Of-Use Filtration


Authors: Aiwen Wu (Entegris, Inc. — United States), Hareen Bayana (Entegris GmbH — Germany), Philippe Foubert (imec — Belgium), Andrea Chacko and Douglas Guererro (Brewer Science, Inc. — United States). This paper describes efforts to leverage different filtration parameters, including retention ratings and membrane materials, to understand their impact on EUV underlayer coating defe... » read more

Probing UPF Dynamic Objects


This paper presents a new low-power verification methodology that makes it possible to continuously monitor the dynamic properties of UPF objects and utilize the information to develop custom low-power verification environments. Based on UPF information model concepts, it allows querying of any dynamic properties of UPF objects through a Tcl API and passing object information on to appropriatel... » read more

Artificial Intelligence For Sustainable And Energy Efficient Buildings


According to the goals of Europe’s green deal missions, the continent strives for becoming carbon neutral by 2050. Since buildings are a major contributor to the overall consumption of energy, improving their energy efficiency can be a key to a more sustainable and greener Europe. On the way towards zero-emission buildings, several challenges have to be met: In modern energy systems, several ... » read more

Demystifying MIPI C-PHY / D-PHY Subsystem


The newest member of the MIPI PHY family, the C-PHY, arrived in October 2014 to a mixture of excitement and apprehension. How would this new C-PHY compare to the MIPI D-PHY and M-PHY? What would differentiate the C-PHY, and would it be compatible enough with the D-PHY so that both could coexist in a hybrid subsystem? Now, years later, the answers are clear. This article will lay out... » read more

The Benefits Of Using Embedded Sensing Fabrics In AI Devices


AI chips, regardless of the application, are not regular ASICs and tend to be very large, this essentially means that AI chips are reaching the reticle limits in-terms of their size. They are also usually dominated by an array of regular structures and this helps to mitigate yield issues by building in tolerance to defect density due to the sheer number of processor blocks. The reason behind... » read more

Chip-Package Co-Analysis Using Ansys RedHawk-CPA


Ansys RedHawk-CPA is an integrated chip–package co-analysis solution that enables quick and accurate modeling of the package layout for inclusion in on-chip power integrity simulations using Ansys RedHawk. With RedHawk-CPA a designer can perform static IR drop analysis and AC hotspot analysis of the package layout following RedHawk static and dynamic analyses respectively. To ensure a reliab... » read more

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