category: Whitepapers

category: IoT, Security & Automotive

Guide To Application Security: What To Look For And Why
By Synopsys - 06 Jan, 2021 - Comments: 0

Does your organization do software development in-house? If you’d like to learn more about application security but don’t know where to start, this white paper will arm you with development and security fundamentals. Inside you'll find: Key concepts, terminology, and why DevSecOps and cloud development matters The trade-offs of different AppSec tools (e.g., SAST, DAST, IAST) and ... » read more

Evaluate ESD Robustness With Cell-Based P2P/CD Verification
By Mentor, a Siemens Business - 21 Dec, 2020 - Comments: 0

Detecting and verifying an ESD structure can be challenging for designers without specialized ESD experience. The Calibre PERC reliability platform offers cell-based P2P and CD checks that can be used to quickly, accurately, and easily evaluate ESD robustness without the need for advanced ESD expertise. To read more, click here. » read more

How 5G Is Influencing Silicon Design
By Synopsys - 21 Dec, 2020 - Comments: 0

5G is introducing a wide array of challenges in next-generation SoCs that go well beyond high bandwidth wireless. These include increasing system bandwidth, lowering SoC latency, and reducing power significantly for the connected internet of things. Using trusted standards-based IP and proven processing and analog IP at the most aggressive process technology nodes is needed to bring 5G to marke... » read more

Chiplets And Heterogeneous Packaging Are Changing System Design And Analysis
By Cadence - 21 Dec, 2020 - Comments: 0

In the domain of electronic product design, solely relying on process shrink as the primary driver of product innovation and improved system performance is no longer a viable approach. The cost and complexity associated with advanced nodes has everyone looking for alternatives to the traditional monolithic system on chip (SoC). The path most are taking leads to the world of “More than Moore�... » read more

A Collaborative Data Model For AI/ML In EDA
By Si2 - 21 Dec, 2020 - Comments: 0

This work explores industry perspectives on: Machine Learning and IC Design Demand for Data Structure of a Data Model A Unified Data Model: Digital and Analog examples Definition and Characteristics of Derived Data for ML Applications Need for IP Protection Unique Requirements for Inferencing Models Key Analysis Domains Conclusions and Proposed Future Work Abstra... » read more

Mythic Case Study
By Codasip - 21 Dec, 2020 - Comments: 0

Mythic, the provider of a unique AI compute platform, was designing an innovative intelligence processing unit (IPU) and found themselves in need of a small, power-efficient, yet programmable core to take care of specific supporting functions. As no off-the-shelf core would exactly match the needs and customization proved challenging, Mythic eventually opted for a complete solution by Codasip. ... » read more

Novel Etch Technologies Utilizing Atomic Layer Process For Advanced Patterning
By TEL - 17 Dec, 2020 - Comments: 0

We demonstrated a high selective and anisotropic plasma etch of Si3N4 and SiC. The demonstrated process consists of a sequence of ion modification and chemical dry removal steps. The Si3N4 etch with H ion modification showed a high selectivity to SiO2 and SiC films. In addition, we have developed selective etch of SiC with N ion modification. On the other hand, in the patterning etch processes,... » read more

Process Variation Analysis of Device Performance Using Virtual Fabrication
By Coventor - 16 Dec, 2020 - Comments: 0

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. W... » read more

New RDL-First PoP Fan-Out Wafer-Level Package Process With Chip-to-Wafer Bonding Technology
By Amkor - 16 Dec, 2020 - Comments: 0

Fan-Out Wafer-Level Interposer Package-on Package (PoP) design has many advantages for mobile applications such as low power consumption, short signal path, small form factor, and heterogeneous integration for multifunctions. In addition, it can be applied in various package platforms, including PoP, System-in-Package (SiP), and Chip Scale Package (CSP). These advantages come from advanced inte... » read more

A Production-Worthy Fan-Out Solution — ASE FOCoS Chip Last
By ASE - 16 Dec, 2020 - Comments: 0

The 5th Generation (5G) wireless systems popularity will push the package development into a high performance and heterogeneous integration form. For high I/O density and high performance packages, the promising Fan Out Chip on Substrate (FOCoS) provides a solution to match outsourced semiconductor assembly and testing (OSAT) capability. FOCoS is identified the Fan Out (FO) package, which can f... » read more

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