category: Whitepapers

category: IoT, Security & Automotive

Application Driven Network-on Chip Architecture Exploration & Refinement for a Complex SoC
By Arteris - 04 Nov, 2020 - Comments: 0

Peer-reviewed technical journal article from Springer's "Design Automation for Embedded Systems Journal."  Summarizes the various features a NoC is required to implement to be integrated in modern SoCs. Describes a top-down approach, based on the progressive refinement of the NoC description from its functional specification (Sect. 4) to its verification (Sect. 8) Click here to read more. ... » read more

Trust Assurance And Security Verification Of Semiconductor IPs And ICs
By OneSpin Solutions - 28 Oct, 2020 - Comments: 0

Connected autonomous vehicles, 5G networks, Internet-of-things (IoT) devices, defense systems, and critical infrastructure use ASIC and FPGA SoCs running artificial intelligence algorithms or other complex software stacks. Vulnerable or tampered ICs can compromise the safety of people and the confidentiality, integrity, and availability of sensitive information. This paper analyzes the trust an... » read more

Virtual Verification Of Computational Storage Devices
By Mentor, a Siemens Business - 28 Oct, 2020 - Comments: 0

Over recent years, there has been a move to replace hard-disk drive (HDD) storage with solid-state drive (SSD) storage. SDDs are faster, contain no moving parts that can fail or be affected by environmental hazards, and the cost of SSDs has been dropping each year. Unfortunately, the verification of an SSD is quite complex. In particular because of hyperscale datacenter enterprise and client-dr... » read more

Lower Process Nodes Drive Timing Signoff Software Evolution
By Synopsys - 28 Oct, 2020 - Comments: 0

A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff. I... » read more

Clarifying Language/Methodology Confusion
By Aldec - 28 Oct, 2020 - Comments: 0

Engineers working on modern, large FPGA designs face multiple challenges: changing languages, methodologies and tools implementing them. The fact that many designs now contain both hardware and software only add to the confusion. This document tries to clarify the situation. Click here to read more. » read more

Rigid-Flex PCB Bending EM Analysis Using Clarity 3D Solver
By Cadence - 28 Oct, 2020 - Comments: 0

Rigid-Flex PCBs have been used in many modern electronic devices (such as mobile phones, laptops, and wearables, among others), due to their form factor, light weight, and cost-effectiveness. Electromagnetic (EM) analysis of Rigid-Flex PCBs has always been a challenging task for many commercially available 3D numerical solver technologies (FEM and FDTD), due to the complexity in the 3D designs.... » read more

Side Wettable Flanks For Leadless Automotive Packaging
By Amkor - 21 Oct, 2020 - Comments: 0

The MicroLeadFrame (MLF)/Quad Flat No-Lead (QFN) packaging solution is extremely popular in the semiconductor industry. It is used in applications ranging from consumer electronics and communications to those requiring high reliability performance, such as the automotive industry. The wide acceptance of this packaging design is primarily due to its flexible form factors, size, scalability and t... » read more

2019-2020 Mask Maker Survey Results
By eBeam Initiative - 21 Oct, 2020 - Comments: 0

The survey results of the 2019-2020 Mask Maker Survey from the eBeam Initiative. • Multi-Beam and EUV Trends Becoming Visible • 558,834 masks reported by 10 different companies than last year • Masks written with Multi-Beam Mask Writers more than doubled • EUV mask yield reported at 91% • MPC usage increasing at leading edge nodes Click here to see the presentation. » read more

Impact Of EUV Resist Thickness On Local Critical Dimension Uniformities For <30nm CD Via Patterning
By Coventor - 21 Oct, 2020 - Comments: 0

This paper describes the impact of extreme ultraviolet (EUV) resist thickness on <30 nm via local critical dimension uniformity (LCDU) measured during after development inspection (ADI) and after etch inspection (AEI). For the same post-etch CD targets, increasing resist thickness from 40 to 60 nm helped reduced CD variability. This work was performed via virtual fabrication using Coventor�... » read more

SystemVerilog Constraints
By Mentor, a Siemens Business - 14 Oct, 2020 - Comments: 0

This paper looks at two of the most common issues when constraint solver results do not match your intent: Not understanding how Verilog expression evaluation rules apply to interpret the rules of basic algebra and not understanding the affect probability has on choosing solution values. Coding recommendations for improving your code to get better results are provided. To read more, click here. » read more

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