Securing The IoT Begins With Zero-Touch Provisioning At Scale


The path to secured IoT deployments starts with a hardware root-of-trust at the device level, a simple concept that belies the complexity of managing a chain of trust that extends from every edge device to the core of the network. The solution to this management challenge, based on a coordinated effort of domain experts, is a zero touch “chip-to-cloud” provisioning service for certificates-... » read more

Solution Efficiencies For Dynamic Function eXchange Using Abstract Shells


Dynamic Function eXchange (DFX) enables great flexibility within Xilinx® silicon, empowering you to load applications on demand, deliver updates to deployed systems, and reduce power consumption. Platform designs allow for collaboration between groups, where one group can focus on infrastructure and another on hardware acceleration. However, DFX has fundamental flow requirements that lead to l... » read more

Securing 5G And IoT With Fuzzing


5G will revolutionize many industries, with up to 100 times the speed, 100 times the capacity, and one-tenth the latency compared to 4G LTE. But in addition to providing superior performance, 5G expands the attack surface of apps and IoT devices that rely on this next-gen network. In addition to known security exploits, we’re bound to see unknown, novelty attacks. Fuzz testing (or fuzzing)... » read more

Beyond Bug Hunting: Verification Coverage From Safety To Certification


Understanding verification coverage is critical for meeting IC integrity standards and goes well beyond detecting bugs in the design. Without proper verification coverage metrics, meeting strict safety standards and certification may not be achievable. Precise metrics indicate where there are gaps in verification and provide a clear view of the progress being made in the verification effort. Co... » read more

5G Communications


This white paper examines the recent advances that the modeling, simulation, and design automation capabilities in Cadence® AWR® software are helping designers develop the antenna and RF front-end components that are making 5G a reality. This primer offers a breadth of application notes on the innovative wizards and synthesis technologies that enable engineers designing 5G communications syst... » read more

Tape Out On Time With Demand Signoff DRC In P&R


Physical characteristics of devices have become progressively more complex even as design companies pack more devices on each die. Combining these characteristics with ever more demanding chip power, performance, and area (PPA) goals not only result in increased resource utilization but also challenge existing tools/flows/techniques. Adding on-demand signoff-quality DRC verification inside P&R ... » read more

Automated Conversion Of Xilinx Vivado Projects To ALINT-PRO


Aldec's ALINT-PRO design verification solution performs static RTL and design constraints code analysis to uncover critical design issues early in the design cycle. The product helps FPGA developers rise to the challenge of designing large FPGA designs and multiprocessor system on chip devices that include high-capacity and high-performance FPGA hardware. The solution supports running rule c... » read more

Parallel RTL Exploration With Unparalleled Accuracy


Increasing chip complexity and restrictive advanced node rules have made it harder for implementation tools to achieve PPA targets and node entitlements via last-mile optimizations. RTL Architect enables designers to "shift-left" and predict the implementation impact of their RTL. RTL designers, SoC integrators, and IP developers have embraced this fast, predictive technology to give them new i... » read more

RF To Millimeter-Wave Front-End Component Design Trends For 5G Communications


This white paper discusses design challenges and solutions related to the "third wave" of communications, presenting several case studies in which the Cadence AWR Design Environment platform has been used to develop products for 5G and beyond. Examples include a multiband active antenna tuner for cellular internet of things (IoT) machine-type communications (mMTC) applications, a linear power a... » read more

A Methodology To Verify Functionality, Security, And Trust for RISC-V Cores


Modern processor designs present some of the toughest hardware verification challenges. These challenges are especially acute for RISC-V processor core designs, with a wide range of variations and implementations available from a plethora of sources. This paper describes a verification methodology available to both RISC-V core providers and system-on-chip (SoC) teams integrating these cores. It... » read more

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