SVT (Six Stacked Vertical Transistors) SRAM Cell Architecture Introduction: Design And Process Challenges Assessment


This paper presents a new design architecture for advanced logic SRAM cells using six vertical transistors (with carrier transport along the Z direction), stacked one on top of each other. Virtual fabrication technology was used to identify different process integration schemes to enable the fabrication of this architecture with a competitive XY footprint at an advanced logic node: a unit cell ... » read more

Formal Verification Experiences


Several companies have used formal verification to perform silicon bug hunting. That is one of the most advanced usages of formal verification. It is a complex process that includes incorporating multiple sources of information and managing numerous success factors concurrently. This paper will present a “spiral refinement” bug hunt methodology that captures the success factors and guides t... » read more

MIPI D-PHY RX⁺: An Optimized Test Configuration


With the proliferation of the mobile platform, the accelerating adoption of MIPI beyond the traditional mobile platform and into safety related applications, testability of MIPI® PHY is becoming a key requirement. While the D-PHY is the MIPI PHY with the widest adoption in the industry today, the RX+ is a D-PHY receiver configuration optimized for full-speed production testing. The presentatio... » read more

Benefits Of Multilevel Topologies In Power-Efficient Energy Storage Systems (ESS)


In this paper, we discuss the adaption of efficient energy storage systems (ESS) in residential solar and utility-scale applications. System requirements and possible topologies are looked into. For utility-scale, we introduce a multilevel converter topology concept. Click here to read more.   » read more

Load-Pull Analysis For Optimizing PA Performance


In load pull calculations, power amplifiers are going to need harmonic load pull analysis and load pull contours with wideband electromagnetic tuners. Working with RFIC power amplifiers is difficult for the myriad of concurrent design elements that they affect, transmission line voltage, signal interference, and impedance to name a few. In load pull calculations, power amplifiers are going t... » read more

6 Steps To Successful Board Level Reliability Testing


For semiconductor manufacturers entering the automotive environment, the lack of universal qualifications standards often leads to inconsistent reliability expectations. The most efficient solution is to establish a robust and thorough BLR testing plan that is uniquely designed for a specific manufacturer validated by a broad range of industry experiences. 6 Steps to Successful Board Level R... » read more

Automated Traceability Of Requirements In The Design And Verification Process Of Safety-Critical Mixed-Signal Systems


System-level design and verification of safety-critical hardware requires a consistent methodology which complies with industrial safety-standards, for example ISO 26262 for automotive applications. For certification of safety-critical systems, the development process has to implement and enforce a strict traceability of requirements, linking the requirement specification, the design implementa... » read more

Understanding Write Combining On Arm


Write Combining (WC) is a specialized memory type defined by the x86-64 architecture that is used for gathering multiple stores into burst transactions over the system bus. WC is commonly used on x86-64 platforms for interaction with I/O and other peripheral devices. In this whitepaper we provide an overview of the Arm architecture memory types that provide WC-like capabilities. In addition, t... » read more

Advantages Of Picosecond Ultrasonic Technology For Advanced RF Metrology


This paper is from China Semiconductor Technology International Conference (CSTIC). Picosecond Ultrasonics (PULSE Technology) has been widely adopted as the tool-of-record for metal film thickness metrology in semiconductor fabs around the world. It provides unique advantages, such as being a rapid, non-contact, non-destructive technology, and has capabilities for simultaneous multiple layer... » read more

Finding And Fixing Design And Testbench Coding Errors On The Fly


Two things are certain in chip verification: as many bugs as possible must be found and fixed before fabrication, and this must happen as early as possible in the development process. The much-desired “shift left” in verification requires that advanced analysis and debug technologies be available to engineers from the earliest stages of the project. It is preferable that many classes of err... » read more

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