Characterization Of Micro-Bumps For 3DIC Wafer Acceptance Tests


The strong market needs to embed multiple functionalities from different semiconductor processing technologies into a single system continue to drive demands for more advanced 3DIC packaging technologies. Dimensions of copper pillar micro-bumps are consistently reduced in every new technology node to facilitate the 3D stacking of multiple dies so that overall system performance can be improved.... » read more

Residual Stress With EIGER2 R 500K


Many manufacturing processes leave residual stresses which can affect the performance of manufactured components. Compressive stress can be engineered into a metal coating to resist crack propagation, while tensile stress can be exploited to enhance conductivity in semiconductors. Strained materials exhibit changes in atomic spacing which can be detected by X-ray diffraction (XRD) and related t... » read more

In-Line Airborne Particle Sensing Supports Faster Response To Contamination Excursions


Fine particles (less than 5 micrometers in diameter) do not affect most industrial processes, but they can have a disastrous impact on semiconductor manufacturing. From the earliest days, manufacturing facilities have deployed air filtering and recirculation to remove particles from the cleanroom, but particles may still be generated inside process tools, where they can cause defects and yield ... » read more

The Evolving Landscape Of SoC Vulnerabilities And Analog Threats


SoC integrators know that a software-only chip security plan leaves devices open to attack. The more effective way to thwart hackers is to combat both digital and analog threats by incorporating security-focused hardware modules built into the core machine design. This paper describes sources of vulnerabilities to cyber attacks and what infrastructure is needed to secure against them. The So... » read more

Securing The IoT Begins With Zero-Touch Provisioning At Scale


The path to secured IoT deployments starts with a hardware root-of-trust at the device level, a simple concept that belies the complexity of managing a chain of trust that extends from every edge device to the core of the network. The solution to this management challenge, based on a coordinated effort of domain experts, is a zero touch “chip-to-cloud” provisioning service for certificates-... » read more

Solution Efficiencies For Dynamic Function eXchange Using Abstract Shells


Dynamic Function eXchange (DFX) enables great flexibility within Xilinx® silicon, empowering you to load applications on demand, deliver updates to deployed systems, and reduce power consumption. Platform designs allow for collaboration between groups, where one group can focus on infrastructure and another on hardware acceleration. However, DFX has fundamental flow requirements that lead to l... » read more

Securing 5G And IoT With Fuzzing


5G will revolutionize many industries, with up to 100 times the speed, 100 times the capacity, and one-tenth the latency compared to 4G LTE. But in addition to providing superior performance, 5G expands the attack surface of apps and IoT devices that rely on this next-gen network. In addition to known security exploits, we’re bound to see unknown, novelty attacks. Fuzz testing (or fuzzing)... » read more

Beyond Bug Hunting: Verification Coverage From Safety To Certification


Understanding verification coverage is critical for meeting IC integrity standards and goes well beyond detecting bugs in the design. Without proper verification coverage metrics, meeting strict safety standards and certification may not be achievable. Precise metrics indicate where there are gaps in verification and provide a clear view of the progress being made in the verification effort. Co... » read more

5G Communications


This white paper examines the recent advances that the modeling, simulation, and design automation capabilities in Cadence® AWR® software are helping designers develop the antenna and RF front-end components that are making 5G a reality. This primer offers a breadth of application notes on the innovative wizards and synthesis technologies that enable engineers designing 5G communications syst... » read more

Tape Out On Time With Demand Signoff DRC In P&R


Physical characteristics of devices have become progressively more complex even as design companies pack more devices on each die. Combining these characteristics with ever more demanding chip power, performance, and area (PPA) goals not only result in increased resource utilization but also challenge existing tools/flows/techniques. Adding on-demand signoff-quality DRC verification inside P&R ... » read more

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