Automated Traceability Of Requirements In The Design And Verification Process Of Safety-Critical Mixed-Signal Systems


System-level design and verification of safety-critical hardware requires a consistent methodology which complies with industrial safety-standards, for example ISO 26262 for automotive applications. For certification of safety-critical systems, the development process has to implement and enforce a strict traceability of requirements, linking the requirement specification, the design implementa... » read more

Understanding Write Combining On Arm


Write Combining (WC) is a specialized memory type defined by the x86-64 architecture that is used for gathering multiple stores into burst transactions over the system bus. WC is commonly used on x86-64 platforms for interaction with I/O and other peripheral devices. In this whitepaper we provide an overview of the Arm architecture memory types that provide WC-like capabilities. In addition, t... » read more

Advantages Of Picosecond Ultrasonic Technology For Advanced RF Metrology


This paper is from China Semiconductor Technology International Conference (CSTIC). Picosecond Ultrasonics (PULSE Technology) has been widely adopted as the tool-of-record for metal film thickness metrology in semiconductor fabs around the world. It provides unique advantages, such as being a rapid, non-contact, non-destructive technology, and has capabilities for simultaneous multiple layer... » read more

Finding And Fixing Design And Testbench Coding Errors On The Fly


Two things are certain in chip verification: as many bugs as possible must be found and fixed before fabrication, and this must happen as early as possible in the development process. The much-desired “shift left” in verification requires that advanced analysis and debug technologies be available to engineers from the earliest stages of the project. It is preferable that many classes of err... » read more

Systematic Methodology To Solve Reset Challenges In Automotive SoCs


Modern automotive SoCs typically contain multiple asynchronous reset signals to ensure systematic functional recovery from unexpected situations and faults. This complex reset architecture leads to a new set of problems such as possible reset domain crossing (RDC) issues. The conventional clock domain and CDC verification methodologies cannot identify such critical bugs. In this paper, we prese... » read more

Xilinx AI Engines And Their Applications


This white paper explores the architecture, applications, and benefits of using Xilinx's new AI Engine for compute intensive applications like 5G cellular and machine learning DNN/CNN. 5G requires between five to 10 times higher compute density when compared with prior generations; AI Engines have been optimized for DSP, meeting both the throughput and compute requirements to deliver the hig... » read more

mmWave Chip, Package, And Board Beamforming Solutions


RF front-end architectures grow more complex with each generation of communication systems. To accommodate these architectures, more densification and miniaturization is taking place with electronic systems implemented through innovations in system-in-package (SiP) design. 5G data rates exceeding 1GB/s will be supported by the available bandwidth in the millimeter-wave (mmWave) spectrum and ... » read more

CISO’s Guide To Sensitive Data Protection


Emerging data protection and privacy laws are causing organizations to scramble to implement strategies that address regulatory compliance and data security governance. And the SolarWinds software supply chain attack, in which attackers inserted a malicious back door into its network software release that later led to sensitive data exposure, further underscores the need to secure the DevSecOps... » read more

Using Cliosoft SOS Design Management Platform In The Cloud


In this eBook, we will talk about the various scenarios for how designers can leverage Cliosoft’s SoC design management platform in the cloud (Amazon Web Services and Google Cloud Platform) to successfully tapeout their SoCs. Click here to access the eBook. » read more

Exercising State Machines with Command Sequences


Almost every non-trivial design contains at least one state machine, and exercising that state machine through its legal states, state transitions, and the different reasons for state transitions is key to verifying the design’s functionality. In some cases, we can exercise a state machine simply as a side-effect of performing normal operations on the design. In other cases, the state machine... » read more

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