Challenges In 3D Resists

3D integration straddles the line between CMOS fabs and packaging and assembly houses. Depending on the structure being fabricated, the most appropriate process might be more “CMOS-like” or more “package-like.”

For example, in CMOS fabs lithography means spin-on photoresist, exposed by a high precision stepper. Inherent in this approach is an assumption that the wafer surface is flat. Thanks to the near-universal use of chemical mechanical planarization (CMP), integrated circuits usually are flat, at least to within the limits of spin coating models. Structures for 3D integration, on the other hand, often are not. Through-silicon vias (TSVs) drill deep into the silicon wafer, and a separate lithography step may be needed to open the bottoms of these vias. Interposers and redistribution wiring often have significant topography, with deep cavities and elevated wires.

In a presentation at the 2012 Electronic Components and Technology Conference, researchers from the Fraunhofer Institute pointed out that the standard model for spin-on resist thickness breaks down if surface topography exceeds 40 microns. As the wafer spins, larger features act like boulders in a stream, with a thick accumulation of resist “upstream” and a low-coverage eddy “downstream.” Interactions between adjacent features can lead to complex, non-uniform coating patterns.

Spray coating of resists is one potential solution, implemented in tools like EV Group’s EVG150XT resist coating and developing system for 3D structures. Still, the viscosity and drying rate of the resist will affect coverage uniformity. Vertical features such as via or cavity sidewalls are very difficult to coat. If the resist is too viscous, it will dry before spreading over the entire surface. Not viscous enough, and it won’t adhere to vertical surfaces. Nor can a liquid resist bridge openings, as might be desirable for some MEMS and TSV applications.

In the CMOS world, conformal hard masks are sometimes used to protect topographically difficult structures. These are used in some 3D applications as well, but each deposition and removal cycle increases the packaging cost.

Meanwhile, the printed circuit board industry sees dry-film resists as a versatile solution to topographic complexity. Dry film, a photosensitive polymer sandwiched between layers of plastic film, can conform to large features and bridge openings. In MEMS devices, it is often used as a mold material for deposition of free-standing structures. But here, too, there are limits. Dry films generally cannot achieve the resolution or conformality of liquid resists.

And so, as with most aspects of 3D integration, it is difficult to generalize. CMOS image sensors and stacked memories face different constraints from heterogenous sensor-circuit combinations. Ultimately, the industry is likely to see a range of lithography schemes, with CMOS-like processes for smaller, flatter geometries giving way to other alternatives for larger, more three-dimensional structures.