A novel configurable last level cache IP with per-master way partitioning, scratchpad RAM allocation, AXI interfaces and functional safety mechanisms.
As artificial intelligence (AI) and autonomous vehicle systems have grown in complexity, system performance needs have begun to conflict with latency and power consumption requirements. This dilemma is forcing semiconductor engineers to re-architect their system-on-chip (SoC) designs to provide more scalable levels of performance, flexibility, efficiency, and integration. From the edge to data centers, these needs require a rethink of memory organization and structures, and careful consideration of how on-chip dataflow is enabled and managed between the various high-performance IP blocks and off-chip memories. This paper describes a novel configurable last level cache IP, CodaCache, that provides an easy-to-integrate solution giving system architects the capability to configure and adapt the IP to their specific needs. Key technologies implemented in this IP are per-master way partitioning, scratchpad RAM allocation, AXI interfaces and functional safety mechanisms.
Authors: Kurt Shuler, VP of Marketing at Arteris IP, and JP Loison, Corporate Application Engineer at Arteris IP.
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