Evaluation of Cache Replacement Policies Using Various Typical Simulation Approaches


A technical paper titled “Improving the Representativeness of Simulation Intervals for the Cache Memory System” was published by researchers at Complutense University of Madrid, imec, and KU Leuven. Abstract: "Accurate simulation techniques are indispensable to efficiently propose new memory or architectural organizations. As implementing new hardware concepts in real systems is often not... » read more

CodaCache: Helping to Break the Memory Wall


As artificial intelligence (AI) and autonomous vehicle systems have grown in complexity, system performance needs have begun to conflict with latency and power consumption requirements. This dilemma is forcing semiconductor engineers to re-architect their system-on-chip (SoC) designs to provide more scalable levels of performance, flexibility, efficiency, and integration. From the edge to data ... » read more

A Primer On Last-Level Cache Memory For SoC Designs


System-on-chip (SoC) architects have a new memory technology, last level cache (LLC), to help overcome the design obstacles of bandwidth, latency and power consumption in megachips for advanced driver assistance systems (ADAS), machine learning, and data-center applications. LLC is a standalone memory that inserts cache between functional blocks and external memory to ease conflicting requireme... » read more

Layering Protocol Verification


Layering protocols are modeled using layering structures that mirror the protocol layers. There are significant challenges in modelling verification components for layering protocols such as (1) reuse, (2) scalability, (3) controllability, and (4)observability. Furthermore, there may be requirements for complex test scenarios where a great deal of interaction is required between test sequence e... » read more