Directed Self-Assembly Grows Up

By Mark LaPedus
At last year’s SPIE Advanced Lithography conference, Christopher Bencher, a member of the technical staff at Applied Materials, said the buzz surrounding directed self-assembly (DSA) technology resembled the fervor generated at the famous Woodstock rock concert in 1969.

This was clearly evident from the tumultuous and free-flowing movement that threatened the status quo over the potential use of DSA, an alternative patterning technology that enables fine pitches through the use of block copolymers.

A year later, DSA has joined the lithography establishment. Amazingly, within a short time span, DSA has moved from a mere curiosity item into the R&D mode at GlobalFoundries, IBM, Intel, Samsung and TSMC. “Companies are taking DSA seriously,” said Bencher, a DSA expert. “If you compared it to last year, we are now in the pre-competitive stage with DSA. The people in DSA have all grown up and are now wearing suits and ties.”

For some time, most chipmakers have kept their DSA efforts shrouded in secrecy. At the recent SPIE event, however, chipmakers finally provided the first glimpse of their initial work and results.

Based on the early findings, DSA still has a way to go before it moves into IC production. Chipmakers are just getting their arms around the problems. And they are still experimenting with an assortment of fab tools, flows, chemistries and design methodologies.

Still, the initial findings are also promising, providing a clue to where DSA is heading. For example, using DSA, Intel demonstrated 28nm structures. Separately, GlobalFoundries devised 28nm fins with DSA. IBM developed a silicon-on-insulator (SOI) DSA flow. And Samsung may have found the path towards sub-20nm DRAMs.

It’s still unclear when DSA will reach production. The projections range from the 14nm to 7nm nodes. “If you ask different people, you will get different answers,” said Joy Cheng, a research staff member at IBM.

DSA: From the lab to the fab?
DSA is not a next-generation lithography (NGL) tool per se, but rather it is a complementary and double-patterning scheme. DSA is also disruptive and threatens the status quo, because the process isn’t dependent on traditional and costly lithography. Many of the key processing steps are conducted in an existing wafer track system.

There are two basic types of DSA methods: graphoepitaxy and chemical epitaxy. In graphoepitaxy, a guide is patterned using existing lithography tools. Using a track, the guide is spin-coated, rinsed and spin-coated again with copolymers. The copolymers self-assemble and the guide is then etched. In chemical epitaxy, self-assembly is guided by lithographically determined chemical patterns.

In theory, DSA is attractive because it could reduce the overall cost of lithography. And compared to EUV, DSA requires less R&D funding.

“We don’t need billions of dollars,” said Ralph Dammel, chief technology officer for AZ Electronic Materials, a supplier of materials for DSA and other applications. “Materials development is inherently cheaper than tool development. The current funding is probably adequate to get the industry going for the 14nm node with DSA. If we’re talking about high chi polymers, which will be needed for the 10nm node and beyond, the industry should think about different funding mechanisms. But even so, we are not talking about huge sums.”

Meanwhile, over the last year, Albany Nanotech, CEA-Leti and IMEC have set up 300mm R&D pilot lines for DSA. Major chipmakers are doing their R&D work within these organizations. “Basically, DSA is still in the R&D stage,” said Charles Pieczulewski, director of strategic marketing for Sokudo, a wafer track supplier. “The industry is still working through the bugs with the materials.”

Going forward, the challenge is to bring DSA into the IC design and production phases. “The main challenge is device integration,” said Ben Rathsack, strategic marketing and technology manager at Tokyo Electron Ltd., the world’s largest wafer track supplier.

Last year, Applied’s Bencher listed defectivity as the top challenge for DSA, followed in order by registration, design flexibility and positional accuracy. For 2013, positional accuracy—or the ability to align the block copolymers in the proper place—has moved to the biggest challenge for DSA, Bencher said.

Bencher expects memory makers will be the early adopters for DSA, followed by logic and foundry vendors. The prediction is based on the ability to generate IC designs using DSA. “You hear people saying: ‘We need a whole design ecosystem to enable DSA.’ That might be true for logic, but these are the last people that would implement DSA. This is because you need the most flexible designs in logic,” Bencher said. “Memory makers don’t really need that whole design ecosystem. They need maybe 1% of the EDA ecosystem, compared to the logic people.”

Currently, there are several design approaches for DSA. One idea is using 1D gridded arrays, but the problems are obvious. “Designers don’t want to be restricted to having contacts only on a grid or vias on a grid,” Bencher said.

Another concept is laying down a sea of holes or fins on a pattern. “In the chemical epitaxy approach, you make holes everywhere to start with. Later, you will do a lithographic step, where you select which ones you want to keep and which ones you want to get rid of. But the problem is that the aerial image can be very sloppy,” he said.

And in another approach, Stanford University is developing an arbitrary design methodology for DSA using an alphabet soup of characters. In this approach, positional accuracy with the contact holes is the biggest challenge.

Chipmakers tip DSA efforts
Design is just one of the many challenges facing silicon foundries with DSA. For example, GlobalFoundries has set up a DSA R&D line at Albany Nanotech. Using chemical epitaxy, the company demonstrated three-stack, 28nm silicon fin structures. It also is experimenting with a graphoepitaxy flow.

“The advantage for using chemical epitaxy is that there is no loss for aerial density,” said Richard Farrell, a principal engineer at GlobalFoundries. “The advantage in working with graphoepitaxy is that it involves a relatively simple process. Some of the challenges that we face for graphoepitaxy is the translation of the edge roughness into the DSA pattern itself. For line/space, we need temperatures above 200 degrees. This has additional constraints on the lithographic performance of the resists.”

Bringing up DSA in a fab is another issue. “First, we have to deal with fab-compatibility in DSA processing,” he said. “There are contamination issues. In pattern transfer, we need to think about balance reflectivity and the use of planarization.”

Despite the challenges, chipmakers are moving full speed ahead with DSA—and for good reason. For example, NAND flash vendors are pushing 193nm immersion and multi-patterning to the limits, but suppliers are in dire need of a new solution. “EUV lithography and double patterning are widely known (to handle) sub-20nm patterning,” said Jaewoo Nam, a lithography engineer at Samsung, at the recent SPIE conference. “But EUV has some limitations. The pattern resolution for EUV is 16nm only. The cost is huge. Double patterning is also very complicated.”

Using DSA, Samsung is exploring the possibility of developing DRAMs at 18nm. Samsung’s initial goal with DSA is to devise 20nm contact holes. In a DSA R&D line, the company has implemented a graphoepitaxy flow using block PS-b-PMMA materials. With a proprietary treatment process, Samsung has improved the CD distribution by 28%, Nam said.

Like Samsung, Intel also is bullish about DSA. “DSA sparks off a dozen different ideas,” said Sam Sivakumar, a fellow and director of lithography at Intel. The possible applications for DSA include contact holes, vias, and the back-end-of-the-line (BEOL) flow, he said.

Intel is conducting its DSA R&D at IMEC. Last year, IMEC set up a 300mm DSA R&D line, which consists of TEL’s track systems. Using the University of Wisconsin flow, Intel devised a three-layer, 28nm stack. The stack includes an interconnect, via and a metal 1 layer.

Intel started with staggered contact hole arrays on a grid at 50nm to 55nm. After the pattern transfer process, the holes were reduced to 26nm to 22nm, representing a 35% shrink. With a blended DSA formula from JSR, Intel obtained the targeted resolutions with good results, said Todd Younkin, a lithography materials researcher at Intel. However, the results were less conclusive with traditional block copolymers, which are provided by both AZ Electronic Materials and Dow.

Another R&D organization, CEA-Leti, last year set up a 300mm DSA pilot line, which uses Sokudo’s track systems. Using PS-b-PMMA from Arkema and a graphoepitaxy process flow, CEA-Leti achieved resolutions from 35nm to 10nm, said Raluca Tiron, a senior scientist at CEA-Leti. “We showed good uniformity with three sigma around 2nm,” she said. “After the optimization of the process, we counted 6,800 divisional points on the wafer. We only found five missing contacts.”

PS-b-PMMA is expected to hit the wall at 10nm, meaning the industry must develop next-generation high chi DSA materials. Others see it differently. “We think we can extend PS-b-PMMA down to the 7nm node,” said Laurent Pain, lithography lab manager at CEA-Leti.

Another player, IBM, is involved in several different DSA efforts. In one effort, IBM demonstrated a larger-pitch 42nm flow, which could one day enable the development of smaller chips based on SOI. In this experiment, IBM used both the Almaden and University of Wisconsin flows, which enabled 42nm and 28nm resolutions. “If we can do self-assembly at 42nm, we can do assembly at smaller pitches,” said Chi-Chun Liu, a research staff member at IBM.